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/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt20 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
21 <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
22 <&cru SCLK_MAC_RX>: clock gate for RX
23 <&cru SCLK_MAC_TX>: clock gate for TX
24 <&cru SCLK_MACREF>: clock gate for RMII referce clock
25 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
26 <&cru ACLK_GMAC>: AXI clock gate for GMAC
27 <&cru PCLK_GMAC>: APB clock gate for GMAC
38 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
40 can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
[all …]
/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
43 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44 <&cru SCLK_UPHY0_TCPDPHY_REF>;
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
48 resets = <&cru SRST_UPHY0>,
49 <&cru SRST_UPHY0_PIPE_L00>,
50 <&cru SRST_P_UPHY0_TCPHY>;
67 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68 <&cru SCLK_UPHY1_TCPDPHY_REF>;
[all …]
/Documentation/devicetree/bindings/clock/
Drockchip,rk3128-cru.txt9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
24 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3128-cru";
56 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
Drockchip,rk3188-cru.txt9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
60 clocks = <&cru SCLK_UART0>;
Drockchip,rk3399-cru.txt9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
50 cru: clock-controller@ff760000 {
51 compatible = "rockchip,rk3399-cru";
63 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
Drockchip,rk3308-cru.txt9 - compatible: CRU should be "rockchip,rk3308-cru"
22 preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
40 cru: clock-controller@ff500000 {
41 compatible = "rockchip,rk3308-cru";
55 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
Drockchip,rk3036-cru.txt9 - compatible: should be "rockchip,rk3036-cru"
22 preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
37 cru: cru@20000000 {
38 compatible = "rockchip,rk3036-cru";
55 clocks = <&cru SCLK_UART0>;
Drockchip,px30-cru.txt9 - compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
10 - compatible: CRU should be "rockchip,px30-cru"
23 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
46 cru: clock-controller@ff2b0000 {
47 compatible = "rockchip,px30-cru";
Drockchip,rk3228-cru.txt9 - compatible: should be "rockchip,rk3228-cru"
22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3228-cru";
57 clocks = <&cru SCLK_UART0>;
Drockchip,rv1108-cru.txt9 - compatible: should be "rockchip,rv1108-cru"
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
40 cru: cru@20200000 {
41 compatible = "rockchip,rv1108-cru";
58 clocks = <&cru SCLK_UART0>;
Drockchip,rk3288-cru.txt9 - compatible: should be "rockchip,rk3288-cru"
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
60 clocks = <&cru SCLK_UART0>;
Drockchip,rk3328-cru.txt9 - compatible: should be "rockchip,rk3328-cru"
22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
39 cru: clock-controller@ff440000 {
40 compatible = "rockchip,rk3328-cru";
57 clocks = <&cru SCLK_UART0>;
Drockchip,rk3368-cru.txt9 - compatible: should be "rockchip,rk3368-cru"
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
43 cru: clock-controller@ff760000 {
44 compatible = "rockchip,rk3368-cru";
60 clocks = <&cru SCLK_UART0>;
/Documentation/devicetree/bindings/pci/
Drockchip-pcie-ep.txt45 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
53 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
Drockchip-pcie-host.txt85 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
86 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
94 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
104 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
105 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
106 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
/Documentation/devicetree/bindings/usb/
Drockchip,dwc3.txt26 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
27 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
43 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
44 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
/Documentation/devicetree/bindings/media/
Drockchip-rga.txt28 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
31 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
Drockchip-vpu.txt28 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
39 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
/Documentation/devicetree/bindings/crypto/
Drockchip-crypto.txt23 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
24 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
26 resets = <&cru SRST_CRYPTO>;
/Documentation/devicetree/bindings/display/rockchip/
Dcdn-dp-rockchip.txt19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
41 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
42 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
44 assigned-clocks = <&cru SCLK_DP_CORE>;
48 resets = <&cru SRST_DPTX_SPDIF_REC>;
Drockchip-vop.txt53 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
55 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
/Documentation/devicetree/bindings/pinctrl/
Dbrcm,bcm4708-pinmux.txt10 Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
18 - offset: offset of pin registers in the CRU block
41 cru@100 {
/Documentation/devicetree/bindings/iio/adc/
Drockchip-saradc.txt31 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
33 resets = <&cru SRST_SARADC>;
/Documentation/devicetree/bindings/thermal/
Drockchip-thermal.txt31 - rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
41 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
43 resets = <&cru SRST_TSADC>;
/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.txt64 clocks = <&cru 8>, <&cru 18>;
75 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
78 assigned-clocks = <&cru SCLK_EMMC>;

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