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/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
[all …]
Dnvidia,tegra20-gmi.txt56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
[all …]
/Documentation/m68k/
Dbuddha-driver.rst147 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
152 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
155 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
158 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
161 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
167 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
170 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
176 781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.
180 system: Sometimes two more clock cycles are inserted by the
[all …]
/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.txt25 - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
37 mrvl,clk-delay-cycles = <31>;
49 mrvl,clk-delay-cycles = <0x1F>;
/Documentation/devicetree/bindings/c6x/
Dclocks.txt24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/Documentation/devicetree/bindings/misc/
Difm-csi.txt14 - ifm,csi-wait-cycles: sensor bus wait cycles
34 ifm,csi-wait-cycles = <0>;
/Documentation/misc-devices/
Disl29003.rst54 0: 2^16 cycles (default)
55 1: 2^12 cycles
56 2: 2^8 cycles
57 3: 2^4 cycles
/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt22 - ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
24 cycles for SR2_WTCNT_VALUE).
79 ti,clock-cycles = <8>;
99 ti,clock-cycles = <16>;
126 ti,clock-cycles = <16>;
/Documentation/ABI/testing/
Dsysfs-bus-iio-impedance-analyzer-ad593332 Number of output excitation cycles (settling time cycles)
Dsysfs-bus-event_source-devices-events5 /sys/devices/cpu/events/stalled-cycles-frontend
7 /sys/devices/cpu/events/stalled-cycles-backend
9 /sys/devices/cpu/events/cpu-cycles
/Documentation/devicetree/bindings/iio/adc/
Davia-hx711.yaml14 - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval
15 and up to 3 cycles for selection of the input channel and gain for the
/Documentation/devicetree/bindings/display/exynos/
Dsamsung-fimd.txt46 - cs-setup: clock cycles for the active period of address signal is enabled
49 - wr-setup: clock cycles for the active period of CS signal is enabled until
52 - wr-active: clock cycles for the active period of CS is enabled.
54 - wr-hold: clock cycles for the active period of CS is disabled until write
/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
74 channel-reset-timeout-cycles = <0x500>;
/Documentation/devicetree/bindings/ata/
Dsata_highbank.txt27 cycles to transmit before sending an SGPIO pattern
29 cycles to transmit after sending an SGPIO pattern
/Documentation/devicetree/bindings/input/touchscreen/
Dti-tsc-adc.txt42 ADC clock cycles. Charge delay value should be large
57 clock cycles to wait after applying the
64 ADC clock cycles to sample (to hold
/Documentation/devicetree/bindings/devfreq/
Drk3399_dmc.txt33 for PD_IDLE DFI clock cycles.
38 for SR_IDLE * 1024 DFI clock cycles (DFI
46 sr_mc_gate_idle*1024 DFI clock cycles.
51 for srpd_lite_idle * 1024 DFI clock cycles.
58 clock cycles.
/Documentation/
Dstatic-keys.txt302 1,474,374,262 cycles # 1.723 GHz ( +- 0.17% )
303 <not supported> stalled-cycles-frontend
304 <not supported> stalled-cycles-backend
319 1,432,559,428 cycles # 1.703 GHz ( +- 0.18% )
320 <not supported> stalled-cycles-frontend
321 <not supported> stalled-cycles-backend
331 saved .2% on instructions, and 2.8% on cycles and 1.4% on elapsed time.
/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
161 * 2 pixclk cycles.
/Documentation/devicetree/bindings/display/
Dssd1307fb.txt26 - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
27 - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
/Documentation/admin-guide/perf/
Darm-ccn.rst52 ccn/cycles/ [Kernel PMU event]
57 / # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \
/Documentation/devicetree/bindings/sound/
Dics43432.txt6 64 clock cycles in each stereo output frame; 24 of the 32 available bits
Dcs35l33.txt54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
/Documentation/devicetree/bindings/pwm/
Dpwm-zx.txt9 calculating period and duty cycles.
/Documentation/devicetree/bindings/input/
Dstmpe-keypad.txt9 - st,scan-count : Scanning cycles elapsed before key data is updated

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