Searched +full:d +full:- +full:tlb +full:- +full:size (Results 1 – 13 of 13) sorted by relevance
| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
[all …]
|
| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
[all …]
|
| /Documentation/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
[all …]
|
| /Documentation/x86/ |
| D | pti.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 Once enabled at compile-time, it can be disabled at boot with the
31 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
65 Protection against side-channel attacks is important. But,
70 a. Each process now needs an order-1 PGD instead of order-0.
72 b. The 'cpu_entry_area' structure must be 2MB in size and 2MB
86 non-PTI SYSCALL entry code, so requires mapping fewer
[all …]
|
| /Documentation/virt/kvm/ |
| D | mmu.txt | 10 - correctness: the guest should not be able to determine that it is running
13 a particular implementation such as tlb size)
14 - security: the guest must not be able to touch host memory not assigned
16 - performance: minimize the performance penalty imposed by the mmu
17 - scaling: need to scale to large memory and large vcpu guests
18 - hardware: support the full range of x86 virtualization hardware
19 - integration: Linux memory management code must be in control of guest memory
22 - dirty tracking: report writes to guest memory to enable live migration
23 and framebuffer-based displays
24 - footprint: keep the amount of pinned kernel memory low (most memory
[all …]
|
| /Documentation/networking/ |
| D | bonding.txt | 7 Corrections, HA extensions : 2000/10/03-15 :
8 - Willy Tarreau <willy at meta-x.org>
9 - Constantine Gavrilov <const-g at xpert.com>
10 - Chad N. Tindel <ctindel at ieee dot org>
11 - Janice Girouard <girouard at us dot ibm dot com>
12 - Jay Vosburgh <fubar at us dot ibm dot com>
16 - Mitch Williams <mitch.a.williams at intel.com>
29 the original tools from extreme-linux and beowulf sites will not work
114 -----------------------------------------------
130 -------------------------------------
[all …]
|
| /Documentation/driver-api/ |
| D | vfio.rst | 2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
36 ---------------------------
42 as allowing a device read-write access to system memory imposes the
55 For instance, an individual device may be part of a larger multi-
59 could be anything from a multi-function PCI device with backdoors
[all …]
|
| /Documentation/ia64/ |
| D | err_inject.rst | 50 #corrected, data cache, hier-2, physical addr(assigned by tool code).
55 #corrected, data cache, hier-2, physical addr(assigned by tool code).
60 #recoverable, DTR0, hier-2.
111 #define ERR_DATA_BUFFER_SIZE 3 // Three 8-byte.
114 #define PATH_FORMAT "/sys/devices/system/cpu/cpu%d/err_inject/"
128 sprintf(fn, "%d.log", cpu);
132 return -1;
152 u64 mode : 3, /* 0-2 */
153 err_inj : 3, /* 3-5 */
154 err_sev : 2, /* 6-7 */
[all …]
|
| /Documentation/filesystems/ |
| D | proc.txt | 1 ------------------------------------------------------------------------------
3 ------------------------------------------------------------------------------
9 ------------------------------------------------------------------------------
11 Kernel version 2.4.0-test11-pre4
12 ------------------------------------------------------------------------------
16 -----------------
23 1.1 Process-Specific Subdirectories
35 3 Per-Process Parameters
36 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
38 3.2 /proc/<pid>/oom_score - Display current oom-killer score
[all …]
|
| /Documentation/ |
| D | DMA-API-HOWTO.txt | 10 with example pseudo-code. For a concise description of the API, see
11 DMA-API.txt.
23 The virtual memory system (TLB, page tables, etc.) translates virtual
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
49 +-------+ +------+ +------+
52 C +-------+ --------> B +------+ ----------> +------+ A
54 +-----+ | | | | bridge | | +--------+
55 | | | | +------+ | | | |
58 +-----+ +-------+ +------+ +------+ +--------+
[all …]
|
| /Documentation/powerpc/ |
| D | ultravisor.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
75 +---+---+---+---------------+
79 +---+---+---+---------------+
81 +---+---+---+---------------+
[all …]
|
| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
56 Documentation/firmware-guide/acpi/debug.rst for more information about
92 size limitation.
119 Disable auto-serialization of AML methods
[all …]
|
| /Documentation/RCU/ |
| D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
[all …]
|