Searched full:defines (Results 1 – 25 of 369) sorted by relevance
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| /Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 30 - rockchip,pd_idle : Configure the PD_IDLE value. Defines the
35 - rockchip,sr_idle : Configure the SR_IDLE value. Defines the
42 - rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
48 - rockchip,srpd_lite_idle : Defines the self-refresh power down idle
54 - rockchip,standby_idle : Defines the standby idle period in which
60 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
65 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
70 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
76 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
80 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
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| /Documentation/devicetree/bindings/ata/ |
| D | nvidia,tegra124-ahci.txt | 11 - interrupts : Defines the interrupt used by SATA
29 - hvdd-supply : Defines the SATA HVDD regulator
30 - vddio-supply : Defines the SATA VDDIO regulator
31 - avdd-supply : Defines the SATA AVDD regulator
32 - target-5v-supply : Defines the SATA 5V power regulator
33 - target-12v-supply : Defines the SATA 12V power regulator
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 37 - devbus,turn-off-ps: Defines the time during which the controller does not
43 - devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
52 - devbus,acc-first-ps: Defines the time delay from the negation of
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
62 - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
71 - devbus,rd-hold-ps: Defines the time between the last data sample to the
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
89 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
91 is active. This parameter defines the setup time of
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| /Documentation/ABI/obsolete/ |
| D | sysfs-class-net-mesh | 49 Defines the bandwidth which is propagated by this
56 Defines the state of the gateway features. Can be
63 Defines the selection criteria this node will use
70 Defines the penalty which will be applied to an
77 Defines the isolation mark (and its bitmask) which
102 Defines the interval in milliseconds in which batman
109 Defines the routing procotol this mesh instance
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| D | sysfs-class-net-batman-adv | 8 Defines the interval in milliseconds in which batman
29 Defines the throughput value to be used by B.A.T.M.A.N. V
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cpus.txt | 17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some architecture categories not defined
32 snooped. This property defines a bitmask which selects the bit
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-funnel | 5 Description: (RW) Enables the slave ports and defines the hold time of the
12 Description: (RW) Defines input port priority order.
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| D | sysfs-bus-event_source-devices-format | 8 Each attribute of this group defines the 'hardware' bitmask
19 Defines contents of attribute that occupies bits 1,6-10,44 of
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| D | sysfs-bus-coresight-devices-etm3x | 119 Description: (RW) Defines which event triggers a trace.
177 Description: (RW) Defines the event that causes the sequencer to transition
184 Description: (RW) Defines the event that causes the sequencer to transition
191 Description: (RW) Defines the event that causes the sequencer to transition
198 Description: (RW) Defines the event that causes the sequencer to transition
205 Description: (RW) Defines the event that causes the sequencer to transition
212 Description: (RW) Defines the event that causes the sequencer to transition
232 Description: (RW) Defines an event that requests the insertion of a timestamp
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | tda998x.txt | 21 - video-ports: 24 bits value which defines how the video controller
25 The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2].
26 The second value defines the tda998x AP_ENA reg content when the DAI
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| /Documentation/devicetree/bindings/extcon/ |
| D | extcon-arizona.txt | 31 defines.
33 specified as per the ARIZONA_MICD_TIME_XXX defines.
44 The first cell defines the accessory detection pin, zero will use MICDET1
50 ARIZONA_GPSW_XXX defines.
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| /Documentation/devicetree/bindings/mfd/ |
| D | da9063.txt | 24 - regulators : This node defines the settings for the LDOs and BUCKs.
49 - rtc : This node defines settings for the Real-Time Clock associated with
54 - onkey : This node defines the OnKey settings for controlling the key
66 - watchdog : This node defines settings for the Watchdog timer associated
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| /Documentation/media/ |
| D | ca.h.rst.exceptions | 6 # struct ca_slot_info defines
15 # struct ca_descr_info defines
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| /Documentation/sphinx/ |
| D | parse-headers.pl | 25 my %defines;
84 $defines{$s} = "\\ :ref:`$s <$n>`\\ ";
157 delete $defines{$1} if (exists($defines{$1}));
204 $defines{$old} = $new if (exists($defines{$old}));
233 print Data::Dumper->Dump([\%defines], [qw(*defines)]) if (%defines);
270 foreach my $r (keys %defines) {
271 my $s = $defines{$r};
341 enums and defines and create cross-references to a Sphinx book.
377 It is capable of identifying defines, functions, structs, typedefs,
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| /Documentation/devicetree/bindings/sound/ |
| D | mvebu-audio.txt | 19 The first one is mandatory and defines the internal clock.
20 The second one is optional and defines an external clock.
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| /Documentation/driver-api/rapidio/ |
| D | tsi721.rst | 33 - This parameter defines number of hardware buffer
38 - DMA transactions queue size. Defines number of pending
43 - DMA channel selection mask. Bitmask that defines which hardware
58 - RIO messaging MBOX selection mask. This is a bitmask that defines
84 - defines number of hardware buffer descriptors used by
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| /Documentation/devicetree/bindings/gpio/ |
| D | 8xxx_gpio.txt | 34 - #interrupt-cells: Should be two. Defines the number of integer
37 defines the pin number, the second cell
38 defines additional flags (trigger type,
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ltc2990.txt | 9 The first integer defines the bits 2..0 in the control register. In all
22 The second integer defines the bits 4..3 in the control register. This
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| /Documentation/media/uapi/v4l/ |
| D | colorspaces.rst | 19 you can accurately display that color. A colorspace defines what it
47 standard that defines spectral weighting functions that model the
48 perception of color. Specifically that standard defines functions that
79 defines a colorspace.
102 intensity of the color. So each colorspace also defines a transfer
112 The final piece that defines a colorspace is a function that transforms
155 colorspace standard only defines some, and you have to rely on other
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-ocelot-serdes.txt | 26 The first number defines the input port to use for a given
27 SerDes macro. The second defines the macro to use. They are
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec4.txt | 46 Node defines the base address of the SEC 4 block.
68 Definition: A standard property. Defines the number of cells
74 Definition: A standard property. Defines the number of cells
158 Child of the crypto node defines data processing interface to SEC 4
208 Child node of the crypto node. Defines a register space that
224 Definition: A standard property. Defines the number of cells
231 Definition: A standard property. Defines the number of cells
261 A child node that defines individual RTIC memory regions that are used to
263 The node defines a register that contains the memory address &
311 Node defines address range and the associated
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| D | fsl-sec6.txt | 13 Node defines the base address of the SEC 6 block.
34 Definition: A standard property. Defines the number of cells
40 Definition: A standard property. Defines the number of cells
74 Child of the crypto node defines data processing interface to SEC 6
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| /Documentation/arm/samsung-s3c24xx/ |
| D | suspend.rst | 31 The S3C2410 user manual defines the process of sending the CPU to
105 The S3C2410 specific configuration in `System Type` defines various
129 Defines the size of memory each CRC chunk covers. A smaller value
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| /Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.txt | 97 The following table defines the set of PLL/clock index and ID for Cygnus.
145 The following table defines the set of PLL/clock for Hurricane 2:
161 The following table defines the set of PLL/clock index and ID for Northstar and
192 The following table defines the set of PLL/clock index and ID for Northstar 2.
253 The following table defines the set of PLL/clock index and ID for Stingray.
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | realtek-smi.txt | 6 not use the MDIO protocol. This binding defines how to specify the
35 This defines an interrupt controller with an IRQ line (typically
50 This defines the internal MDIO bus of the SMI device, mostly for the
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