Searched full:delay (Results 1 – 25 of 319) sorted by relevance
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-cadence.txt | 24 They are used to delay the data valid window, and align the window
25 to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
27 - cdns,phy-input-delay-sd-highspeed:
28 Value of the delay in the input path for SD high-speed timing
30 - cdns,phy-input-delay-legacy:
31 Value of the delay in the input path for legacy timing
33 - cdns,phy-input-delay-sd-uhs-sdr12:
34 Value of the delay in the input path for SD UHS SDR12 timing
36 - cdns,phy-input-delay-sd-uhs-sdr25:
37 Value of the delay in the input path for SD UHS SDR25 timing
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| D | sdhci-sprd.txt | 26 PHY DLL delays are used to delay the data valid window, and align the window
29 write line delay value, clock read command line delay value, clock read data
30 positive edge delay value and clock read data negative edge delay value.
31 Each cell's delay value unit is cycle of the PHY clock.
33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
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| D | fsl-imx-esdhc.txt | 25 - fsl,delay-line : Specify the number of delay cells for override mode.
26 This is used to set the clock delay for DLL(Delay Line) on override mode
29 chapter, DLL (Delay Line) section in RM for details.
36 - fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
37 The uSDHC use one delay cell as default increasing step to do tuning process.
38 This property allows user to change the tuning step to more than one delay
40 tuning step can't find the proper delay window within limited tuning retries.
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| D | mtk-sd.txt | 38 - hs400-ds-delay: HS400 DS delay setting
39 - mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
42 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
68 hs400-ds-delay = <0x14015>;
69 mediatek,hs200-cmd-int-delay = <26>;
70 mediatek,hs400-cmd-int-delay = <14>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | mt6358-regulator.txt | 34 regulator-ramp-delay = <12500>;
35 regulator-enable-ramp-delay = <0>;
43 regulator-ramp-delay = <6250>;
44 regulator-enable-ramp-delay = <200>;
52 regulator-ramp-delay = <50000>;
53 regulator-enable-ramp-delay = <250>;
60 regulator-ramp-delay = <6250>;
61 regulator-enable-ramp-delay = <200>;
69 regulator-ramp-delay = <6250>;
70 regulator-enable-ramp-delay = <200>;
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| D | mt6397-regulator.txt | 31 regulator-ramp-delay = <12500>;
32 regulator-enable-ramp-delay = <200>;
40 regulator-ramp-delay = <12500>;
41 regulator-enable-ramp-delay = <115>;
49 regulator-ramp-delay = <12500>;
50 regulator-enable-ramp-delay = <115>;
59 regulator-ramp-delay = <12500>;
60 regulator-enable-ramp-delay = <115>;
69 regulator-ramp-delay = <12500>;
70 regulator-enable-ramp-delay = <115>;
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| D | mt6323-regulator.txt | 27 regulator-ramp-delay = <12500>;
36 regulator-ramp-delay = <25000>;
51 regulator-enable-ramp-delay = <90>;
60 regulator-enable-ramp-delay = <185>;
67 regulator-enable-ramp-delay = <185>;
74 regulator-enable-ramp-delay = <185>;
81 regulator-enable-ramp-delay = <216>;
90 regulator-enable-ramp-delay = <216>;
97 regulator-enable-ramp-delay = <216>;
106 regulator-enable-ramp-delay = <216>;
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| D | mt6380-regulator.txt | 24 regulator-ramp-delay = <6250>;
33 regulator-ramp-delay = <6250>;
40 regulator-ramp-delay = <0>;
49 regulator-ramp-delay = <0>;
58 regulator-ramp-delay = <0>;
67 regulator-ramp-delay = <0>;
76 regulator-ramp-delay = <0>;
85 regulator-ramp-delay = <0>;
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| D | anatop-regulator.txt | 14 - anatop-delay-reg-offset: Anatop MFD step time register offset
15 - anatop-delay-bit-shift: Bit shift for the step time register
16 - anatop-delay-bit-width: Number of bits used in the step time register
34 anatop-delay-reg-offset = <0x170>;
35 anatop-delay-bit-shift = <24>;
36 anatop-delay-bit-width = <2>;
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| /Documentation/accounting/ |
| D | delay-accounting.rst | 2 Delay accounting
9 The per-task delay accounting functionality measures
25 delay statistics aggregated for all tasks (or threads) belonging to a
30 aggregate delay statistics into arbitrary groups. To enable this, delay
38 Delay accounting uses the taskstats interface which is described
41 statistics. The delay accounting functionality populates specific fields of
46 for a description of the fields pertaining to delay accounting.
48 delay seen for cpu, sync block I/O, swapin, memory reclaim etc.
51 counter (say cpu_delay_total) for a task will give the delay
61 commands to be run and the corresponding delay statistics to be displayed. It
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| D | taskstats-struct.rst | 13 2) Delay accounting fields
16 /* Delay accounting fields start */
20 /* Delay accounting fields end */
38 6) Extended delay accounting fields for memory reclaim
97 2) Delay accounting fields::
99 /* Delay accounting fields start
101 * All values, until the comment "Delay accounting fields end" are
102 * available only if delay accounting is enabled, even though the last
105 * xxx_count is the number of delay values recorded
106 * xxx_delay_total is the corresponding cumulative delay in nanoseconds
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| /Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.txt | 14 reset. After a delay specified by active-delay, the GPIO is set to
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
40 - active-delay: Delay (default 100) to wait after driving gpio active [ms]
41 - inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms]
42 - wait-delay: Delay (default 3000) to wait after completing restart
51 active-delay = <100>;
52 inactive-delay = <100>;
53 wait-delay = <3000>;
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| D | gpio-poweroff.txt | 12 triggering positive edge triggered power off. After a delay of 100ms,
15 delay the GPIO is driver active again. If the power is still on and
16 the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted.
30 - active-delay-ms: Delay (default 100) to wait after driving gpio active
31 - inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive
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| /Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
39 ti,c64x+pll-lock-delay = <80000>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | brcm,sr-thermal.txt | 11 - polling-delay: Max number of milliseconds to wait between polls.
34 polling-delay-passive = <0>;
35 polling-delay = <1000>;
46 polling-delay-passive = <0>;
47 polling-delay = <1000>;
58 polling-delay-passive = <0>;
59 polling-delay = <1000>;
70 polling-delay-passive = <0>;
71 polling-delay = <1000>;
82 polling-delay-passive = <0>;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 67 - mpmc,write-enable-delay: Delay from chip select assertion to write
70 - mpmc,output-enable-delay: Delay from chip select assertion to output
73 - mpmc,write-access-delay: Delay from chip select assertion to write
76 - mpmc,read-access-delay: Delay from chip select assertion to read
79 - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
82 - mpmc,turn-round-delay: Delay between access to memory banks in nano
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
112 mpmc,read-enable-delay = <70>;
113 mpmc,page-mode-read-delay = <70>;
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| /Documentation/devicetree/bindings/sound/ |
| D | dmic.txt | 11 - wakeup-delay-ms: Delay (in ms) after enabling the DMIC
12 - modeswitch-delay-ms: Delay (in ms) to complete DMIC mode switch
20 wakeup-delay-ms <50>;
21 modeswitch-delay-ms <35>;
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| /Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.txt | 12 - power-on-delay: delay after turning regulators on [ms]
13 - reset-delay: delay after reset sequence [ms]
14 - init-delay: delay after initialization sequence [ms]
35 power-on-delay= <50>;
36 reset-delay = <100>;
37 init-delay = <100>;
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
50 adi,rx-internal-delay-ps = <1800>;
51 adi,tx-internal-delay-ps = <2200>;
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| D | ti,dp83867.txt | 5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
16 The default strapping will use a delay of 2.00 ns. Thus
18 internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
56 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
57 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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| D | mediatek-dwmac.txt | 21 interface and timing delay.
24 - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
26 - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
28 Both delay properties need to be a multiple of 170 for RGMII interface,
30 Both delay properties need to be a multiple of 550 for MII/RMII interface,
69 mediatek,tx-delay-ps = <1530>;
70 mediatek,rx-delay-ps = <1530>;
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| /Documentation/devicetree/bindings/spi/ |
| D | sh-msiof.txt | 67 - renesas,dtdl : delay sync signal (setup) in transmit mode.
69 0 (no bit delay)
70 50 (0.5-clock-cycle delay)
71 100 (1-clock-cycle delay)
72 150 (1.5-clock-cycle delay)
73 200 (2-clock-cycle delay)
75 - renesas,syncdl : delay sync signal (hold) in transmit mode.
77 0 (no bit delay)
78 50 (0.5-clock-cycle delay)
79 100 (1-clock-cycle delay)
[all …]
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| /Documentation/devicetree/bindings/serial/ |
| D | rs485.txt | 9 - rs485-rts-delay: prop-encoded-array <a b> where:
10 * a is the delay between rts signal and beginning of data sent in milliseconds.
11 it corresponds to the delay before sending data.
12 * b is the delay between end of data sent and rts signal in milliseconds
13 it corresponds to the delay after sending data and actual release of the line.
29 rs485-rts-delay = <0 200>; // in milliseconds
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| /Documentation/admin-guide/device-mapper/ |
| D | delay.rst | 2 dm-delay
5 Device-Mapper's "delay" target delays reads and/or writes
10 <device> <offset> <delay> [<write_device> <write_offset> <write_delay>
24 echo "0 `blockdev --getsz $1` delay $1 0 500" | dmsetup create delayed
31 echo "0 `blockdev --getsz $1` delay $1 0 0 $2 0 500" | dmsetup create delayed
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| /Documentation/devicetree/bindings/input/ |
| D | lpc32xx-key.txt | 12 - nxp,debounce-delay-ms: Debounce delay in ms
13 - nxp,scan-delay-ms: Repeated scan period in ms
31 nxp,debounce-delay-ms = <3>;
32 nxp,scan-delay-ms = <34>;
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