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/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt26 Describes the main PLL clock output (before POSTDIV). The node name must
33 Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/Documentation/devicetree/bindings/x86/
Dce4100.txt30 A "cpu" node describes one logical processor (hardware thread).
44 This node describes the in-core peripherals. Required property:
49 This node describes the PCI bus on the SoC. Its property should be
/Documentation/devicetree/bindings/powerpc/
Dibm,powerpc-cpu-features.txt12 This device tree binding describes CPU features available to software, with
104 This property describes the privilege levels and/or software components
118 This property describes the HV privilege support required to enable the
137 This property describes the OS privilege support required to enable the
154 property describes the bit number in the HFSCR register that the
167 property describes the bit number in the FSCR register that the
180 This property describes the bit number that should be set in the ELF AUX
/Documentation/ABI/testing/
Dsysfs-hypervisor-xen17 Describes mode that Xen's performance-monitoring unit (PMU)
32 Describes Xen PMU features (as an integer). A set bit indicates
Dsysfs-bus-i3c53 This entry describes the BCR of the master controller driving
63 This entry describes the DCR of the master controller driving
75 This entry describes the PID of the master controller driving
87 This entry describes the HDRCAP of the master controller
/Documentation/devicetree/bindings/net/
Dmarvell-orion-net.txt9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
/Documentation/devicetree/bindings/c6x/
Ddscr.txt64 This property describes the bitfields used to control the state of devices.
65 Each tuple describes a range of identical bitfields used to control one or
80 This property describes the bitfields used to provide device state status
81 for device states controlled by the DSCR. Each tuple describes a range of
/Documentation/arm/
Dsetup.rst5 The following document describes the kernel initialisation parameter
55 This describes the character position of cursor on VGA console, and
85 This describes the kernel virtual start address and size of the
/Documentation/devicetree/bindings/mailbox/
Dqcom,apcs-kpss-global.txt4 This binding describes the APCS "global" block found in various Qualcomm
41 The following example describes the APCS HMSS found in MSM8996 and part of the
/Documentation/devicetree/bindings/phy/
Duniphier-usb3-ssphy.txt3 This describes the devicetree bindings for PHY interfaces built into
6 this describes about Super-Speed PHY.
Duniphier-usb3-hsphy.txt3 This describes the devicetree bindings for PHY interfaces built into
6 this describes about High-Speed PHY.
/Documentation/devicetree/bindings/remoteproc/
Dqcom,adsp.txt89 describes the communication edge, channels and devices related to the ADSP.
95 The following example describes the resources needed to boot control the
130 The following example describes the resources needed to boot control the
/Documentation/devicetree/bindings/input/touchscreen/
Dts4800-ts.txt8 describes the FPGA's syscon registers.
/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.txt6 differences. Hence, this document describes closely related but different
30 Tegra HW documentation describes a unified naming convention for all GPIOs
43 describes the port-level mapping. In that file, the naming convention for ports
92 order the HW manual describes them. The number of entries required varies
/Documentation/devicetree/bindings/leds/backlight/
Dgpio-backlight.txt5 - gpios: describes the gpio that is used for enabling/disabling the backlight.
/Documentation/networking/
Dnf_flowtable.txt4 This documentation describes the software flowtable infrastructure available in
31 This is represented in Fig.1, which describes the classic forwarding path
106 acceleration" that describes how things were before this infrastructure was
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-cpucfg.txt3 The MSCM IP contains multiple sub modules, this binding describes the first
/Documentation/devicetree/bindings/power/supply/ab8500/
Dchargalg.txt3 The properties below describes the node for chargalg driver.
Dbtemp.txt3 The properties below describes the node for btemp driver.
/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm21664.txt4 This document describes the device tree bindings for boards with the BCM21664
Dbrcm,bcm23550.txt4 This document describes the device tree bindings for boards with the BCM23550
/Documentation/firmware-guide/
Dindex.rst7 This section describes the ACPI subsystem in Linux from firmware perspective.
/Documentation/admin-guide/hw-vuln/
Dindex.rst5 This section describes CPU vulnerabilities and provides an overview of the
/Documentation/filesystems/ext4/
Dchecksums.rst26 The following table describes the data elements that go into each type
27 of checksum. The checksum function is whatever the superblock describes
/Documentation/devicetree/bindings/display/imx/
Dldb.txt48 or a display-timings node that describes the video timings for the connected
66 - display-timings : A node that describes the display timings as defined in
69 This describes how the color bits are laid out in the

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