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/Documentation/gpu/
Damdgpu-dc.rst2 drm/amd/display - Display Core (DC)
7 Because it is partially shared with other operating systems, the Display Core
10 1. **Display Core (DC)** contains the OS-agnostic components. Things like
12 2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
24 ``Display Core initialized with <version number here>``
26 AMDgpu Display Manager
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
21 - A KMS driver that supports the display controllers as well as a number of
64 The display hardware has remained mostly backwards compatible over the various
68 Display Controllers
71 Tegra SoCs have two display controllers, each of which can be associated with
72 zero or more outputs. Outputs can also share a single display controller, but
73 only if they run with compatible display timings. Two display controllers can
75 on two outputs don't match. A display controller is modelled as a CRTC in KMS
78 On Tegra186, the number of display controllers has been increased to three. A
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Di915.rst6 models) integrated GFX chipsets with both Intel display and rendering
13 This section covers core driver infrastructure used by both the display
67 Display Hardware Handling
70 This section covers everything related to the display hardware including
72 display, output probing and related topics.
79 its own tailor-made infrastructure for executing a display configuration
85 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
88 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
91 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
94 Display FIFO Underrun Reporting
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Dkomeda-kms.rst4 drm/komeda Arm display driver
7 The drm/komeda driver supports the Arm display processor D71 and later products,
11 Overview of D71 like display IPs
14 From D71, Arm display IP begins to adopt a flexible and modularized
15 architecture. A display pipeline is made up of multiple individual and
34 for layer scaling, or connected to compositor and scale the whole display
40 Compositor blends multiple layers or pixel data flows into one single display
44 the display frame first and and then write to memory.
58 Final stage of display pipeline, Timing controller is not for the pixel
59 handling, but only for controlling the display timing.
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/Documentation/devicetree/bindings/display/
Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
34 display-timings {
Dsimple-framebuffer.yaml4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
15 the bootloader, with the assumption that the display hardware has
23 If the devicetree contains nodes for the display hardware used by a
25 display, which contains a phandle pointing to the primary display
30 It is advised to add display# aliases to help the OS determine how
31 to number things. If display# aliases are used, then if the simplefb
32 node contains a display property then the /aliases/display# path
33 must point to the display hw node the display property points to,
38 to it, or to the primary display hw node, as with display#
39 aliases. If display aliases are used then it should be set to the
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Dmxsfb.txt22 lcdif1: display-controller@2220000 {
45 - display: phandle to display node (see below for details)
47 * display node
54 - display-timings: Refer to binding doc display-timing.txt for details.
63 display: display {
67 display-timings {
Drepaper.txt4 - compatible: "pervasive,e1144cs021" for 1.44" display
5 "pervasive,e1190cs021" for 1.9" display
6 "pervasive,e2200cs021" for 2.0" display
7 "pervasive,e2271cs021" for 2.7" display
32 display {
51 pervasive,thermal-zone = "display";
Datmel,lcdc.txt17 - display: a phandle pointing to the display node
20 - display: a display node is required to initialize the lcd panel
22 - default-mode: a videomode within the display with timing parameters
36 display = <&display0>;
50 Atmel LCDC Display
66 display0: display {
74 display-timings {
Dssd1307fb.txt17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,com-seq: Display uses sequential COM pin configuration
23 - solomon,com-lrremap: Display uses left-right COM pin remap
24 - solomon,com-invdir: Display uses inverted COM pin scan direction
25 - solomon,com-offset: Number of the COM pin wired to the first display line
37 - solomon,area-color-enable: Display uses color mode
38 - solomon,low-power. Display runs in low power mode
Dtruly,nt35597.txt1 Truly model NT35597 DSI display driver
3 The Truly NT35597 is a generic display driver, currently only configured
4 for use in the 2K display on the Qualcomm SDM845 MTP board.
7 - compatible: should be "truly,nt35597-2K-display"
17 - mode-gpios: phandle of the gpio for choosing the mode of the display
30 compatible = "truly,nt35597-2K-display";
/Documentation/devicetree/bindings/display/rockchip/
Drockchip-drm.txt5 vop devices or other display interface nodes that comprise the
9 - compatible: Should be "rockchip,display-subsystem"
10 - ports: Should contain a list of phandles pointing to display interface port
12 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
16 display-subsystem {
17 compatible = "rockchip,display-subsystem";
/Documentation/devicetree/bindings/display/panel/
Dilitek,ili9322.txt23 - pixelclk-active: see display/panel/display-timing.txt
24 - de-active: see display/panel/display-timing.txt
25 - hsync-active: see display/panel/display-timing.txt
26 - vsync-active: see display/panel/display-timing.txt
37 panel: display@0 {
Dpanel-common.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
7 title: Common Properties for Display Panels
15 display panels. It doesn't constitue a device tree binding specification by
50 Display rotation in degrees counter clockwise (0,90,180,270)
55 # Display Timings
59 Most display panels are restricted to a single resolution and
60 require specific display timings. The panel-timing subnode expresses those
61 timings as specified in the timing subnode section of the display timing
63 Documentation/devicetree/bindings/display/panel/display-timing.txt.
94 # Many display panels can be controlled through pins driven by GPIOs. The nature
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/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.txt4 that can display one or more lines of text. It exposes an M6800 bus interface,
18 - display-height-chars: Height of the display, in character cells,
19 - display-width-chars: Width of the display, in character cells.
28 with 1 or 2 lines, and display-width-chars for displays with more than 2
43 display-height-chars = <2>;
44 display-width-chars = <16>;
/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-fb.txt11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
13 Additional, the display node has to define properties:
16 A display node may optionally define
34 display = <&display0>;
44 display-timings {
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
14 multiplexer in the front to select any of the four IPU display
20 the display interface selector clocks, as described in
48 or a display-timings node that describes the video timings for the connected
49 LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
62 display-timings are used instead.
64 Optional properties (required if display-timings are used):
66 - display-timings : A node that describes the display timings as defined in
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Dfsl-imx-drm.txt5 IPU or other display interface nodes that comprise the graphics subsystem.
8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,display-subsystem";
113 Parallel display support
117 - compatible: Should be "fsl,imx-parallel-display"
119 - interface-pix-fmt: How this display is connected to the
120 display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
122 - edid: verbatim EDID data block describing attached display.
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/Documentation/devicetree/bindings/display/sunxi/
Dsun4i-drm.txt1 Allwinner A10 Display Pipeline
4 The Allwinner A10 Display pipeline is composed of several components
7 For all connections between components up to the TCONs in the display
74 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
212 TCON TOPs main purpose is to configure whole display pipeline. It determines
217 It allows display pipeline to be configured in very different ways:
296 Display Engine Backend
299 The display engine backend exposes layers and sprites to the
304 * allwinner,sun4i-a10-display-backend
305 * allwinner,sun5i-a13-display-backend
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/Documentation/ABI/testing/
Dsysfs-platform-asus-laptop1 What: /sys/devices/platform/asus_laptop/display
6 This file allows display switching. The value
13 Ex: - 0 (0000b) means no display
29 Some models like the W1N have a LED display that can be
30 used to display several items of information.
31 To control the LED display, use the following :
33 where T control the 3 letters display, and DDD the 3 digits display.
/Documentation/devicetree/bindings/powerpc/fsl/
Ddiu.txt1 * Freescale Display Interface Unit
13 - edid : verbatim EDID data block describing attached display.
15 program the display controller.
18 display@2c000 {
26 display@2100 {
/Documentation/devicetree/bindings/clock/
Dsun9i-de.txt1 Allwinner A80 Display Engine Clock Control Binding
9 - clocks: phandle to the clocks feeding the display engine subsystem.
11 - "mod": the display engine module clock
13 - "bus": the bus clock for the whole display engine subsystem
15 - resets: phandle to the reset control for the display engine subsystem.
Dsun8i-de2.txt1 Allwinner Display Engine 2.0/3.0 Clock Control Binding
14 - clocks: phandle to the clocks feeding the display engine subsystem.
16 - "mod": the display engine module clock (on A83T it's the DE PLL)
17 - "bus": the bus clock for the whole display engine subsystem
19 - resets: phandle to the reset control for the display engine subsystem.
/Documentation/devicetree/bindings/display/exynos/
Dexynos7-decon.txt1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
3 DECON (Display and Enhancement Controller) is the Display Controller for the
34 - display-timings: timing settings for DECON, as described in document [1].
38 [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
/Documentation/arm/omap/
Ddss.rst2 OMAP2/3 Display Subsystem
7 TV-out and multiple display support, but there are lots of small improvements
47 flexible way to enable non-common multi-display configuration. In addition to
49 managers. These can be used when updating a display with CPU or system DMA.
53 There exist several display technologies and standards that support audio as
65 certain configurations audio is not supported (e.g., an HDMI display using a
67 the current configuration of the display supports audio.
70 parameters of the display. In order to make the function independent of any
108 dynamic display architecture.
135 the overlay is smaller than the display.
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