Searched +full:dma +full:- +full:names (Results 1 – 25 of 279) sorted by relevance
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| /Documentation/devicetree/bindings/dma/ |
| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
7 - compatible: should include both "arm,pl330" and "arm,primecell".
8 - reg: physical base address of the controller and length of memory mapped
10 - interrupts: interrupt number to the cpu.
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
18 - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
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| D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "sprd,sc9860-dma".
7 - reg: Should contain DMA registers location and length.
8 - interrupts: Should contain one interrupt shared by all channel.
9 - #dma-cells: must be <1>. Used to represent the number of integer
11 - #dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
13 - clocks: Should contain a clock specifier for each entry in clock-names.
18 apdma: dma-controller@20100000 {
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| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - #dma-channels : Number of DMA channels supported. Should be 16.
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| D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
4 - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
5 - reg : Should contain registers location and length
6 - interrupts : Should contain the interrupt numbers of DMA channels.
8 - #dma-cells : Must be <1>. The number cell specifies the channel ID.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
19 dma_apbh: dma-apbh@80004000 {
20 compatible = "fsl,imx28-dma-apbh";
26 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
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| D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
5 specific DMA request source can only be multiplexed by any channel of certain
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - reg : Specifies base physical address(s) and size of the eDMA registers.
17 - interrupts : A list of interrupt-specifiers, one for each entry in
18 interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
20 error interrupt(located in the last), no interrupt-names list on
22 - #dma-cells : Must be <2>.
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| D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
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| D | qcom_adm.txt | 1 QCOM ADM DMA Controller
4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
14 - clk
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| /Documentation/devicetree/bindings/serial/ |
| D | mrvl,pxa-ssp.txt | 5 - compatible: Must be one of
6 mrvl,pxa25x-ssp
7 mvrl,pxa25x-nssp
8 mrvl,pxa27x-ssp
9 mrvl,pxa3xx-ssp
10 mvrl,pxa168-ssp
11 mrvl,pxa910-ssp
12 mrvl,ce4100-ssp
14 - reg: The memory base
15 - dmas: Two dma phandles, one for rx, one for tx
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| /Documentation/devicetree/bindings/sound/ |
| D | zte,zx-spdif.txt | 4 - compatible : Must be "zte,zx296702-spdif"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
7 - clock-names: "tx" for the clock to the SPDIF interface.
8 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
9 the core. The core expects one dma channel for transmit.
10 - dma-names : Must be "tx"
12 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
14 * resource-names.txt
15 * clock/clock-bindings.txt
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| D | rockchip,pdm.txt | 5 - compatible: "rockchip,pdm"
6 - "rockchip,px30-pdm"
7 - "rockchip,rk1808-pdm"
8 - "rockchip,rk3308-pdm"
9 - reg: physical base address of the controller and length of memory mapped
11 - dmas: DMA specifiers for rx dma. See the DMA client binding,
12 Documentation/devicetree/bindings/dma/dma.txt
13 - dma-names: should include "rx".
14 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
15 - clock-names: should contain following:
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| D | designware-i2s.txt | 4 - compatible : Must be "snps,designware-i2s"
5 - reg : Must contain the I2S core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's
9 - clock-names : "i2sclk" for the sample rate reference clock.
10 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
11 the core. The core expects one or two dma channels: one for transmit and
13 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
16 - interrupts: The interrupt line number for the I2S controller. Add this
17 parameter if the I2S controller that you are using does not support DMA.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
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| D | adi,axi-spdif-tx.txt | 1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
11 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
12 the core. The core expects one dma channel for transmit.
13 - dma-names : Must be "tx"
15 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
17 * resource-names.txt
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| D | zte,zx-i2s.txt | 4 - compatible : Must be one of:
5 "zte,zx296718-i2s", "zte,zx296702-i2s"
6 "zte,zx296702-i2s"
7 - reg : Must contain I2S core's registers location and length
8 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
10 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
11 the core. The core expects two dma channels for transmit.
12 - dma-names : Must be "tx" and "rx"
14 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
15 the core. The core expects two dma channels if both transmit and receive are
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
21 * resource-names.txt
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| D | allwinner,sun4i-a10-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <maxime.ripard@bootlin.com>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
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| D | sun4i-codec.txt | 4 - compatible: must be one of the following compatibles:
5 - "allwinner,sun4i-a10-codec"
6 - "allwinner,sun6i-a31-codec"
7 - "allwinner,sun7i-a20-codec"
8 - "allwinner,sun8i-a23-codec"
9 - "allwinner,sun8i-h3-codec"
10 - "allwinner,sun8i-v3s-codec"
11 - reg: must contain the registers location and length
12 - interrupts: must contain the codec interrupt
13 - dmas: DMA channels for tx and rx dma. See the DMA client binding,
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| /Documentation/devicetree/bindings/crypto/ |
| D | omap-des.txt | 5 - compatible : Should contain "ti,omap4-des"
6 - ti,hwmods: Name of the hwmod associated with the DES module
7 - reg : Offset and length of the register set for the module
8 - interrupts : the interrupt-specifier for the DES module
9 - clocks : A phandle to the functional clock node of the DES module
10 corresponding to each entry in clock-names
11 - clock-names : Name of the functional clock, should be "fck"
14 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
15 Documentation/devicetree/bindings/dma/dma.txt
16 Each entry corresponds to an entry in dma-names
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| D | atmel-crypto.txt | 8 - compatible : Should be "atmel,at91sam9g46-aes".
9 - reg: Should contain AES registers location and length.
10 - interrupts: Should contain the IRQ line for the AES.
11 - dmas: List of two DMA specifiers as described in
12 atmel-dma.txt and dma.txt files.
13 - dma-names: Contains one identifier string for each DMA specifier
18 compatible = "atmel,at91sam9g46-aes";
23 dma-names = "tx", "rx";
28 - compatible : Should be "atmel,at91sam9g46-tdes".
29 - reg: Should contain TDES registers location and length.
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| D | qcom-qce.txt | 5 - compatible : should be "qcom,crypto-v5.1"
6 - reg : specifies base physical address and size of the registers map
7 - clocks : phandle to clock-controller plus clock-specifier pair
8 - clock-names : "iface" clocks register interface
11 - dmas : DMA specifiers for tx and rx dma channels. For more see
12 Documentation/devicetree/bindings/dma/dma.txt
13 - dma-names : DMA request names should be "rx" and "tx"
17 compatible = "qcom,crypto-v5.1";
22 clock-names = "iface", "bus", "core";
24 dma-names = "rx", "tx";
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| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-usart.txt | 4 - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
7 For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
8 - reg: Should contain registers location and length
9 - interrupts: Should contain interrupt
10 - clock-names: tuple listing input clock names.
12 - clocks: phandles to input clocks.
15 - #size-cells : Must be <0>
16 - #address-cells : Must be <1>
17 - cs-gpios: chipselects (internal cs not supported)
18 - atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)
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| /Documentation/devicetree/bindings/spi/ |
| D | microchip,spi-pic32.txt | 4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
13 ------------------
15 ------------------
17 |-> DMA instance #0
19 |-> DMA instance #1
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| /Documentation/devicetree/bindings/usb/ |
| D | da8xx-usb.txt | 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
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| D | ux500-usb.txt | 4 - compatible : Should be "stericsson,db8500-musb"
5 - reg : Offset and length of registers
6 - interrupts : Interrupt; mode, number and trigger
7 - dr_mode : Dual-role; either host mode "host", peripheral mode "peripheral"
11 - dmas : A list of dma channels;
12 dma-controller, event-line, fixed-channel, flags
13 - dma-names : An ordered list of channel names affiliated to the above
18 compatible = "stericsson,db8500-musb";
21 interrupt-names = "mc";
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
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| /Documentation/devicetree/bindings/mmc/ |
| D | jz4740.txt | 8 - compatible: Should be one of the following:
9 - "ingenic,jz4740-mmc" for the JZ4740
10 - "ingenic,jz4725b-mmc" for the JZ4725B
11 - "ingenic,jz4780-mmc" for the JZ4780
12 - reg: Should contain the MMC controller registers location and length.
13 - interrupts: Should contain the interrupt specifier of the MMC controller.
14 - clocks: Clock for the MMC controller.
17 - dmas: List of DMA specifiers with the controller specific format
18 as described in the generic DMA client binding. A tx and rx
20 - dma-names: RX and TX DMA request names.
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