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/Documentation/devicetree/bindings/iio/humidity/
Dhts221.txt4 - compatible: should be "st,hts221"
5 - reg: i2c address of the sensor / spi cs line
8 - drive-open-drain: the interrupt/data ready line will be configured
9 as open drain, which is useful if several sensors share the same
12 IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
13 when it is not active, whereas a pull-up one is needed when interrupt
15 Refer to pinctrl/pinctrl-bindings.txt for the property description.
16 - interrupts: interrupt mapping for IRQ. It should be configured with
20 Refer to interrupt-controller/interrupts.txt for generic interrupt
28 interrupt-parent = <&gpio0>;
/Documentation/devicetree/bindings/iio/imu/
Dst_lsm6dsx.txt1 * ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors
4 - compatible: must be one of:
14 "st,lsm6ds3tr-c"
16 "st,lsm9ds1-imu"
17 - reg: i2c address of the sensor / spi cs line
20 - st,drdy-int-pin: the pin on the package that will be used to signal
22 - st,pullups : enable/disable internal i2c controller pullup resistors.
23 - drive-open-drain: the interrupt/data ready line will be configured
24 as open drain, which is useful if several sensors share the same
26 (This binding is taken from pinctrl/pinctrl-bindings.txt)
[all …]
Dbmi160.txt1 Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
4 https://www.bosch-sensortec.com/bst/products/all_products/bmi160
7 - compatible : should be "bosch,bmi160"
8 - reg : the I2C address or SPI chip select number of the sensor
9 - spi-max-frequency : set maximum clock frequency (only for SPI)
12 - interrupts : interrupt mapping for IRQ
13 - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
15 - drive-open-drain : set if the specified interrupt pin should be configured as
16 open drain. If not set, defaults to push-pull.
24 interrupt-parent = <&gpio4>;
[all …]
/Documentation/devicetree/bindings/mfd/
Dstmfx.txt1 STMicroelectonics Multi-Function eXpander (STMFX) Core bindings
3 ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
9 - compatible: should be "st,stmfx-0300".
10 - reg: I2C slave address of the device.
11 - interrupts: interrupt specifier triggered by MFX_IRQ_OUT signal.
12 Please refer to ../interrupt-controller/interrupt.txt
15 - drive-open-drain: configure MFX_IRQ_OUT as open drain.
16 - vdd-supply: phandle of the regulator supplying STMFX.
21 compatible = "st,stmfx-0300";
24 interrupt-parent = <&gpioi>;
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-sx150x.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
8 - compatible: should be one of :
19 - reg: The I2C slave address for this device.
21 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
25 - gpio-controller: Marks the device as a GPIO controller.
28 - interrupts: Interrupt specifier for the controllers interrupt.
30 - interrupt-controller: Marks the device as a interrupt controller.
32 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
38 Required properties for pin configuration sub-nodes:
[all …]
Dpinctrl-palmas.txt4 the configuration for Pull UP/DOWN, open drain etc.
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
19 those pin(s), and various pin configuration parameters, such as pull-up,
20 open drain.
32 - ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
35 - ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
[all …]
Dcirrus,madera-pinctrl.txt19 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
22 - pinctrl-names : must be "default"
23 - pinctrl-0 : a phandle to the node containing the subnodes containing default
32 - groups : name of one pin group to configure. One of:
42 - function : name of function to assign to this group. One of:
45 io, dsp-gpio, irq1, irq2,
46 fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock,
47 fllao-clk, fllao-lock,
48 opclk, opclk-async, pwm1, pwm2, spdif,
49 asrc1-in1-lock, asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock,
[all …]
Dnvidia,tegra114-pinmux.txt4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22 - nvidia,drive-type: Integer. Valid range 0...3.
[all …]
Dpinctrl-stmfx.txt1 STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander bindings
3 ST Multi-Function eXpander (STMFX) offers up to 24 GPIOs expansion.
7 - compatible: should be "st,stmfx-0300-pinctrl".
8 - #gpio-cells: should be <2>, the first cell is the GPIO number and the second
9 cell is the gpio flags in accordance with <dt-bindings/gpio/gpio.h>.
10 - gpio-controller: marks the device as a GPIO controller.
11 - #interrupt-cells: should be <2>, the first cell is the GPIO number and the
13 <dt-bindings/interrupt-controller/irq.h>.
14 - interrupt-controller: marks the device as an interrupt controller.
15 - gpio-ranges: specifies the mapping between gpio controller and pin
[all …]
Datmel,at91-pio4-pinctrl.txt7 - compatible: "atmel,sama5d2-pinctrl".
8 - reg: base address and length of the PIO controller.
9 - interrupts: interrupt outputs from the controller, one for each bank.
10 - interrupt-controller: mark the device node as an interrupt controller.
11 - #interrupt-cells: should be two.
12 - gpio-controller: mark the device node as a gpio controller.
13 - #gpio-cells: should be two.
15 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
18 Please refer to pinctrl-bindings.txt in this directory for details of the
31 - pinmux: integer array. Each integer represents a pin number plus mux and
[all …]
Dqcom,pmic-gpio.txt6 - compatible:
10 "qcom,pm8005-gpio"
11 "qcom,pm8018-gpio"
12 "qcom,pm8038-gpio"
13 "qcom,pm8058-gpio"
14 "qcom,pm8916-gpio"
15 "qcom,pm8917-gpio"
16 "qcom,pm8921-gpio"
17 "qcom,pm8941-gpio"
18 "qcom,pm8994-gpio"
[all …]
Dnvidia,tegra210-pinmux.txt4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
33 include/dt-binding/pinctrl/pinctrl-tegra.h.
35 Required subnode-properties:
36 - nvidia,pins : An array of strings. Each string contains the name of a pin or
39 Optional subnode-properties:
[all …]
Dnvidia,tegra124-pinmux.txt4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10 Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12 -- first entry - the drive strength and pad control registers.
13 -- second entry - the pinmux registers
14 -- third entry - the MIPI_PAD_CTRL register
18 include/dt-binding/pinctrl/pinctrl-tegra.h.
19 - nvidia,enable-input: Integer. Enable the pin's input path.
[all …]
Dnvidia,tegra194-pinmux.txt4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
21 include/dt-binding/pinctrl/pinctrl-tegra.h.
23 Required subnode-properties:
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
27 Optional subnode-properties:
[all …]
Dpinctrl-bindings.txt4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
47 pinctrl-0: List of phandles, each pointing at a pin configuration
65 pinctrl-1: List of phandles, each pointing at a pin configuration
68 pinctrl-n: List of phandles, each pointing at a pin configuration
70 pinctrl-names: The list of names to assign states. List entry 0 defines the
78 pinctrl-names = "active", "idle";
79 pinctrl-0 = <&state_0_node_a>;
80 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
85 pinctrl-0 = <&state_0_node_a>;
[all …]
Dlantiq,pinctrl-falcon.txt4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pull-up and open-drain
31 Required subnode-properties:
32 - lantiq,groups : An array of strings. Each string contains the name of a group.
34 - lantiq,function: A string containing the name of the function to mux to the
49 Required subnode-properties:
50 - lantiq,pins : An array of strings. Each string contains the name of a pin.
53 Optional subnode-properties:
[all …]
Dnvidia,tegra30-pinmux.txt4 as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
9 - compatible: "nvidia,tegra30-pinmux"
10 - reg: Should contain the register physical address and length for each of
14 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16 - nvidia,lock: Integer. Lock the pin configuration against further changes
18 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
25 per-pin mux groups:
28 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
29 nvidia,io-reset.
[all …]
Dpinctrl-max77620.txt6 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
11 --------------------------
14 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
15 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
16 <pinctrl-bindings.txt>.
19 sub-node have following properties:
22 ------------------
23 - pins: List of pins. Valid values of pins properties are:
27 -------------------
29 <pinctrl-bindings.txt>. Absence of properties will leave the configuration
[all …]
Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
45 From the datasheet Table 10-2.
83 - atmel,pins: 4 integers array, represents a group of pins mux and config
90 MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
91 Multi-drive is equivalent to open-drain type output.
95 DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
[all …]
/Documentation/devicetree/bindings/iio/gyroscope/
Dnxp,fxas21002c.txt3 http://www.nxp.com/products/sensors/gyroscopes/3-axis-digital-gyroscope:FXAS21002C
6 - compatible : should be "nxp,fxas21002c"
7 - reg : the I2C address of the sensor or SPI chip select number for the
9 - vdd-supply: phandle to the regulator that provides power to the sensor.
10 - vddio-supply: phandle to the regulator that provides power to the bus.
13 - reset-gpios : gpio used to reset the device, see gpio/gpio.txt
14 - interrupts : device support 2 interrupts, INT1 and INT2,
16 See interrupt-controller/interrupts.txt
17 - interrupt-names: should contain "INT1" or "INT2", the gyroscope interrupt
19 - drive-open-drain: the interrupt/data ready line will be configured
[all …]
/Documentation/devicetree/bindings/iio/
Dst-sensors.txt3 The STMicroelectronics sensor devices are pretty straight-forward I2C or
8 - compatible: see the list of valid compatible strings below
9 - reg: the I2C or SPI address the device will respond to
12 - vdd-supply: an optional regulator that needs to be on to provide VDD
14 - vddio-supply: an optional regulator that needs to be on to provide the
16 - st,drdy-int-pin: the pin on the package that will be used to signal
19 - drive-open-drain: the interrupt/data ready line will be configured
20 as open drain, which is useful if several sensors share the same
21 interrupt line. (This binding is taken from pinctrl/pinctrl-bindings.txt)
25 standard bindings from pinctrl/pinctrl-bindings.txt.
[all …]
/Documentation/driver-api/gpio/
Ddriver.rst26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
[all …]
Dconsumer.rst6 it describes the new descriptor-based interface. For a description of the
7 deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
23 - Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
27 - Truly optional GPIOLIB support - where the driver does not really make use
28 of the GPIOs on certain compile-time configurations for certain systems, but
29 will use it under other compile-time configurations. In this case the
33 All the functions that work with the descriptor-based GPIO interface are
43 With the descriptor-based interface, GPIOs are identified with an opaque,
44 non-forgeable handler that must be obtained through a call to one of the
60 see Documentation/driver-api/gpio/board.rst
[all …]
/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
23 If 'aspeed,reset-type=' is not specfied the default is to enable system
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
[all …]
/Documentation/devicetree/bindings/sound/
Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost conerter control source selection.
39 0x00 - Control Port Value
[all …]

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