Searched +full:enable +full:- +full:active +full:- +full:high (Results 1 – 25 of 102) sorted by relevance
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| /Documentation/devicetree/bindings/regulator/ |
| D | tps65132-regulator.txt | 4 - compatible: "ti,tps65132"
5 - reg: I2C slave address
9 device node describe the properties of these regulators. The sub-node
11 -For regulator outp, the sub node name should be "outp".
12 -For regulator outn, the sub node name should be "outn".
14 -enable-gpios:(active high, output) Regulators are controlled by the input pins.
17 -active-discharge-gpios: (active high, output) Some configurations use delay mechanisms
18 on the enable pin, to keep the regulator enabled for some time after
19 the enable signal goes low. This GPIO is used to actively discharge
20 the delay mechanism. Requires specification of ti,active-discharge-time-us
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| D | gpio-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: "regulator.yaml#"
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
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| D | fixed-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: "regulator.yaml#"
26 const: regulator-fixed-clock
28 - clocks
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| D | max8973-regulator.txt | 5 - compatible: must be one of following:
8 - reg: the i2c slave address of the regulator. It should be 0x1b.
15 -maxim,externally-enable: boolean, externally control the regulator output
16 enable/disable.
17 -maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided
18 then externally enable control will be considered.
19 -maxim,dvs-gpio: GPIO which is connected to DVS pin of device.
20 -maxim,dvs-default-state: Default state of GPIO during initialisation.
21 1 for HIGH and 0 for LOW.
22 -maxim,enable-remote-sense: boolean, enable reote sense.
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| /Documentation/devicetree/bindings/display/panel/ |
| D | jdi,lt070me05000.txt | 4 - compatible: should be "jdi,lt070me05000"
5 - vddp-supply: phandle of the regulator that provides the supply voltage
6 Power IC supply (3-5V)
7 - iovcc-supply: phandle of the regulator that provides the supply voltage
9 - enable-gpios: phandle of gpio for enable line
10 LED_EN, LED backlight enable, High active
11 - reset-gpios: phandle of gpio for reset line
12 This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
13 XRES, Reset, Low active
14 - dcdc-en-gpios: phandle of the gpio for power ic line
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| D | samsung,s6e3ha2.txt | 5 - compatible: should be one of:
8 - reg: the virtual channel number of a DSI peripheral
9 - vdd3-supply: I/O voltage supply
10 - vci-supply: voltage supply for analog circuits
11 - reset-gpios: a GPIO spec for the reset pin (active low)
12 - enable-gpios: a GPIO spec for the panel enable pin (active high)
15 - te-gpios: a GPIO spec for the tearing effect synchronization signal
16 gpio pin (active high)
25 vdd3-supply = <&ldo27_reg>;
26 vci-supply = <&ldo28_reg>;
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| D | display-timing.txt | 1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
23 - clock-frequency: display clock in Hz
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| D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
52 - $ref: /schemas/types.yaml#/definitions/uint32
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| D | boe,hv070wsa-100.txt | 1 BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
4 - compatible: should be "boe,hv070wsa-100"
5 - power-supply: regulator to provide the VCC supply voltage (3.3 volts)
6 - enable-gpios: GPIO pin to enable and disable panel (active high)
8 This binding is compatible with the simple-panel binding, which is specified
9 in simple-panel.txt in this directory.
15 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
20 compatible = "boe,hv070wsa-100";
21 power-supply = <&vcc_3v3_reg>;
22 enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| /Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
17 -compatible:
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-74x164.txt | 1 * Generic 8-bits shift register GPIO driver
4 - compatible: Should contain one of the following:
7 - reg : chip select number
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells : Should be two. The first cell is the pin number and
11 0 = active high
12 1 = active low
13 - registers-number: Number of daisy-chained shift registers
16 - enable-gpios: GPIO connected to the OE (Output Enable) pin.
23 gpio-controller;
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| /Documentation/devicetree/bindings/power/supply/ |
| D | max8903-charger.txt | 4 - compatible: "maxim,max8903" for MAX8903 Battery Charger
5 - dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided
6 - uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provid…
9 - cen-gpios: Charge enable pin (active low, output)
10 - chg-gpios: Charger status pin (active low, input)
11 - flt-gpios: Fault pin (active low, output)
12 - dcm-gpios: Current limit mode setting (DC=1 or USB=0, output)
13 - usus-gpios: USB suspend pin (active high, output)
18 max8903-charger {
20 dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | aptina,mt9v111.txt | 2 ----------------------------
4 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
7 The sensor has an active pixel array of 640x480 pixels and can output a number
8 of image resolution and formats controllable through a simple two-wires
12 --------------------
14 - compatible: shall be "aptina,mt9v111".
15 - clocks: reference to the system clock input provider.
18 --------------------
20 - enable-gpios: output enable signal, pin name "OE#". Active low.
21 - standby-gpios: low power state control signal, pin name "STANDBY".
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp8860.txt | 1 * Texas Instruments - lp8860 4-Channel LED Driver
3 The LP8860-Q1 is an high-efficiency LED
4 driver with boost controller. It has 4 high-precision
9 - compatible :
11 - reg : I2C slave address
12 - #address-cells : 1
13 - #size-cells : 0
16 - enable-gpios : gpio pin to enable (active high)/disable the device.
17 - vled-supply : LED supply
20 - reg : 0
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| /Documentation/devicetree/bindings/mfd/ |
| D | twl6040.txt | 3 The TWL6040s are 8-channel high quality low-power audio codecs providing audio,
9 - compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041
10 - reg: must be 0x4b for i2c address
11 - interrupts: twl6040 has one interrupt line connecteded to the main SoC
12 - gpio-controller:
13 - #gpio-cells = <1>: twl6040 provides GPO lines.
14 - #clock-cells = <0>; twl6040 is a provider of pdmclk which is used by McPDM
15 - twl6040,audpwron-gpio: Power on GPIO line for the twl6040
17 - vio-supply: Regulator for the twl6040 VIO supply
18 - v2v1-supply: Regulator for the twl6040 V2V1 supply
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| /Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid"
5 - reg : Should contain registers location and length
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
14 - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for the ST which is the IRQ line
18 - clocks: phandle to input clock.
20 - watchdog: compatible should be "atmel,at91rm9200-wdt"
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
14 bit[0]: polarity (0 for active high and 1 for active low)
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
29 - gpio-ranges:
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| D | pinctrl-bindings.txt | 4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
25 For example, a pin controller may set up its own "active" state when the
47 pinctrl-0: List of phandles, each pointing at a pin configuration
65 pinctrl-1: List of phandles, each pointing at a pin configuration
68 pinctrl-n: List of phandles, each pointing at a pin configuration
70 pinctrl-names: The list of names to assign states. List entry 0 defines the
78 pinctrl-names = "active", "idle";
79 pinctrl-0 = <&state_0_node_a>;
80 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | aspeed-wdt.txt | 4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
23 If 'aspeed,reset-type=' is not specfied the default is to enable system
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
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| /Documentation/devicetree/bindings/sound/ |
| D | nau8825.txt | 6 - compatible : Must be "nuvoton,nau8825"
8 - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
11 - nuvoton,jkdet-enable: Enable jack detection via JKDET pin.
12 - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled,
13 otherwise pin in high impedance state.
14 - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down.
15 - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
17 - nuvoton,vref-impedance: VREF Impedance selection
18 0 - Open
19 1 - 25 kOhm
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.txt | 7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
17 For Tegra210 must contain "nvidia,tegra210-pmc"
18 - reg : Offset and length of the register set for the device
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| /Documentation/devicetree/bindings/media/ |
| D | video-interfaces.txt | 4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
51 It is allowed for multiple endpoints at a port to be active simultaneously,
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
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