Searched +full:external +full:- +full:nodes (Results 1 – 25 of 154) sorted by relevance
1234567
| /Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
|
| D | aspeed,ast2500-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
25 const: aspeed,ast2500-pinctrl
26 aspeed,external-nodes:
[all …]
|
| /Documentation/devicetree/bindings/clock/ |
| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
18 with a single clock output and 1 for nodes with multiple
22 clock-output-names: Recommended to be a list of strings of clock output signal
24 However, the meaning of clock-output-names is domain
32 Clock consumer nodes must never directly reference
33 the provider's clock-output-names property.
[all …]
|
| D | rockchip,rk3368-cru.txt | 9 - compatible: should be "rockchip,rk3368-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| D | rockchip,rk3288-cru.txt | 9 - compatible: should be "rockchip,rk3288-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| D | rockchip,rv1108-cru.txt | 9 - compatible: should be "rockchip,rv1108-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| D | renesas,r9a06g032-sysctrl.txt | 5 - compatible: Must be:
6 - "renesas,r9a06g032-sysctrl"
7 - reg: Base address and length of the SYSCTRL IO block.
8 - #clock-cells: Must be 1
9 - clocks: References to the parent clocks:
10 - external 40mhz crystal.
11 - external (optional) 32.768khz
12 - external (optional) jtag input
13 - external (optional) RGMII_REFCLK
14 - clock-names: Must be:
[all …]
|
| D | amlogic,gxbb-aoclkc.txt | 4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
15 - clocks: list of clock phandle, one for each entry clock-names.
16 - clock-names: should contain the following:
[all …]
|
| D | rockchip,rk3228-cru.txt | 9 - compatible: should be "rockchip,rk3228-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| D | samsung,s3c2443-clock.txt | 9 - compatible: should be one of the following.
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes can use this identifier
22 dt-bindings/clock/s3c2443.h header and can be used in device
25 External clocks:
29 clock-output-names:
[all …]
|
| D | renesas,rcar-usb2-clock-sel.txt | 1 * Renesas R-Car USB 2.0 clock selector
3 This file provides information on what the device node for the R-Car USB 2.0
6 If you connect an external clock to the USB_EXTAL pin only, you should set
10 clock rates to both "usb_extal" and "usb_xtal" nodes.
12 Case 1: An external clock connects to R-Car SoC
13 +----------+ +--- R-Car ---------------------+
14 |External |---|USB_EXTAL ---> all usb channels|
16 +----------+ +-------------------------------+
19 Case 2: An oscillator connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
[all …]
|
| D | rockchip,rk3188-cru.txt | 9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
21 Each clock is assigned an identifier and client nodes can use this identifier
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
27 External clocks:
[all …]
|
| D | rockchip,rk3036-cru.txt | 9 - compatible: should be "rockchip,rk3036-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| D | rockchip,rk3328-cru.txt | 9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
|
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,meta-intc.txt | 1 * Meta External Trigger Controller Binding
4 representation of a Meta external trigger controller.
8 - compatible: Specifies the compatibility list for the interrupt controller.
9 The type shall be <string> and the value shall include "img,meta-intc".
11 - num-banks: Specifies the number of interrupt banks (each of which can
14 - interrupt-controller: The presence of this property identifies the node
17 - #interrupt-cells: Specifies the number of cells needed to encode an
20 - #address-cells: Specifies the number of cells needed to encode an
22 'interrupt-map' nodes do not have to specify a parent unit address.
26 - no-mask: The controller doesn't have any mask registers.
[all …]
|
| /Documentation/devicetree/bindings/regulator/ |
| D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
27 - ti,update-config: define it when LP872X_GENERAL_CFG register should be set
28 - ti,dvs-gpio: GPIO specifier for external DVS pin control of LP872x devices.
[all …]
|
| D | as3722-regulator.txt | 5 --------------------
7 regulator node. The AS3722 is having 7 DCDC step-down regulators as
8 sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these
10 vsup-sd2-supply: Input supply for SD2.
11 vsup-sd3-supply: Input supply for SD3.
12 vsup-sd4-supply: Input supply for SD4.
13 vsup-sd5-supply: Input supply for SD5.
14 vin-ldo0-supply: Input supply for LDO0.
15 vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
16 vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
[all …]
|
| /Documentation/devicetree/bindings/media/ |
| D | renesas,vin.txt | 1 Renesas R-Car Video Input driver (rcar_vin)
2 -------------------------------------------
4 The rcar_vin device provides video input capabilities for the Renesas R-Car
8 with both external synchronization and BT.656 synchronization for the latter.
9 Depending on the instance the VIN input is connected to external SoC pins, or
10 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
12 - compatible: Must be one or more of the following
13 - "renesas,vin-r8a7743" for the R8A7743 device
14 - "renesas,vin-r8a7744" for the R8A7744 device
15 - "renesas,vin-r8a7745" for the R8A7745 device
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
[all …]
|
| D | twl4030-audio.txt | 7 - compatible : must be "ti,twl4030-audio"
9 Optional properties, nodes:
12 - codec { }: Need to be present if the audio functionality is used. Within this
14 - ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts
16 -ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise
17 -ti,hs_extmute: Use external mute for HS pop reduction
18 -ti,hs_extmute_gpio: Use external GPIO to control the external mute
19 -ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
23 - ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if
28 clock-frequency = <2600000>;
[all …]
|
| /Documentation/devicetree/bindings/iio/adc/ |
| D | at91_adc.txt | 4 - compatible: Should be "atmel,<chip>-adc"
6 - reg: Should contain ADC registers location and length
7 - interrupts: Should contain the IRQ line for the ADC
8 - clock-names: tuple listing input clock names.
10 - clocks: phandles to input clocks.
11 - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
13 - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
15 - atmel,adc-vref: Reference voltage in millivolts for the conversions
16 - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
18 - atmel,adc-res-names: Contains one identifier string for each resolution
[all …]
|
| D | xilinx-xadc.txt | 13 - compatible: Should be one of
14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
16 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
18 - reg: Address and length of the register set for the device
19 - interrupts: Interrupt for the XADC control interface.
20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
21 when using the AXI-XADC pcore this must be the clock that provides the
25 - xlnx,external-mux:
26 * "none": No external multiplexer is used, this is the default
28 * "single": External multiplexer mode is used with one
[all …]
|
| /Documentation/devicetree/bindings/display/bridge/ |
| D | ps8622.txt | 1 ps8622-bridge bindings
4 - compatible: "parade,ps8622" or "parade,ps8625"
5 - reg: first i2c address of the bridge
6 - sleep-gpios: OF device-tree gpio specification for PD_ pin.
7 - reset-gpios: OF device-tree gpio specification for RST_ pin.
10 - lane-count: number of DP lanes to use
11 - use-external-pwm: backlight will be controlled by an external PWM
12 - video interfaces: Device node can contain video interface port
13 nodes for panel according to [1].
15 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
[all …]
|
| /Documentation/media/v4l-drivers/ |
| D | davinci-vpbe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------
28 -----------------------
34 Implements creation of video2 and video3 device nodes and
38 Loads up VENC, OSD and external encoders such as ths8200. It provides
40 in the VENC or external sub devices. It also provides
42 using sub device ops. The connection of external encoders to VENC LCD
47 When connected to an external encoder, vpbe controller is also responsible
48 for setting up the interface between VENC and external encoders based on
49 board specific settings (specified in board-xxx-evm.c). This allows
[all …]
|
1234567