Searched full:fifo (Results 1 – 25 of 145) sorted by relevance
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
19 PSC FIFO Controller and b is a field that represents an
23 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
24 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
30 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
35 fsl,mpc512x-psc-fifo node
39 - compatible : Should be "fsl,<soc>-psc-fifo"
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
37 tx-fifo-depth = <0x40>;
38 rx-fifo-depth = <0x40>;
48 tx-fifo-depth = <0x40>;
49 rx-fifo-depth = <0x40>;
60 rx-fifo-depth = <0x20>;
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| D | m_can.txt | 20 RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
32 elements are used for each FIFO/Buffer.
37 Rx FIFO 0 0-64 elements / 0-1152 words
38 Rx FIFO 1 0-64 elements / 0-1152 words
40 Tx Event FIFO 0-32 elements / 0-64 words
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cirrus,clps711x-intc.txt | 24 12: UTXINT1 UART1 transmit FIFO half empty
25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
30 18: SS2TX SSI2 transmit FIFO less than half empty
31 28: UTXINT2 UART2 transmit FIFO half empty
32 29: URXINT2 UART2 receive FIFO half full
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | sii902x.txt | 18 audio fifo. The first integer selects i2s audio pin for the
19 first audio fifo#0 (HDMI channels 1&2), second for fifo#1
21 pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
23 fifo#0 and fifo#1 before mapping a channel to fifo#2. Default
25 fifo #0.
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| /Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc.txt | 62 * fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
63 specified, the default value of the fifo size is determined from the
69 * data-addr: Override fifo address with value provided by DT. The default FIFO reg
72 to set fifo address in device tree.
74 * fifo-watermark-aligned: Data done irq is expected if data length is less than
75 watermark in PIO mode. But fifo watermark is requested to be aligned with data
77 watermark quirk to mark this requirement and force fifo watermark setting
108 fifo-watermark-aligned;
119 fifo-depth = <0x80>;
133 fifo-depth = <0x80>;
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| /Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
35 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
38 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
76 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
78 rx-fifo-size). For Axon, either absent or 2048.
79 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
81 tx-fifo-size). For Axon, either absent or 2048.
115 rx-fifo-size = <1000>;
116 tx-fifo-size = <800>;
140 rx-fifo-size = <16384>;
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| D | altera_tse.txt | 22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
23 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
66 rx-fifo-depth = <2048>;
67 tx-fifo-depth = <2048>;
104 rx-fifo-depth = <2048>;
105 tx-fifo-depth = <2048>;
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| D | ethernet-controller.yaml | 116 rx-fifo-depth:
119 The size of the controller\'s receive fifo in bytes. This is used
120 for components that can have configurable receive fifo sizes,
124 tx-fifo-depth:
127 The size of the controller\'s transmit fifo in bytes. This
128 is used for components that can have configurable fifo sizes.
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| D | adi,adin.yaml | 33 adi,fifo-depth-bits:
35 When operating in RMII mode, this option configures the FIFO depth.
64 adi,fifo-depth-bits = <16>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | cirrus,madera-pinctrl.txt | 54 log1-fifo-ne, log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, log5-fifo-ne,
55 log6-fifo-ne, log7-fifo-ne, log8-fifo-ne,
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| /Documentation/devicetree/bindings/usb/ |
| D | atmel-usb.txt | 100 - atmel,fifo-size: Size of the fifo.
118 atmel,fifo-size = <64>;
124 atmel,fifo-size = <1024>;
132 atmel,fifo-size = <1024>;
140 atmel,fifo-size = <1024>;
147 atmel,fifo-size = <1024>;
154 atmel,fifo-size = <1024>;
162 atmel,fifo-size = <1024>;
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| D | dwc2.txt | 42 - g-rx-fifo-size: size of rx fifo size in gadget mode.
43 - g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode.
44 - g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode.
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| /Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
53 cdns,fifo-depth = <128>;
54 cdns,fifo-width = <4>;
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| /Documentation/devicetree/bindings/dma/ |
| D | stm32-dma.txt | 66 -bit 0-1: DMA FIFO threshold selection
67 0x0: 1/4 full FIFO
68 0x1: 1/2 full FIFO
69 0x2: 3/4 full FIFO
70 0x3: full FIFO
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| /Documentation/devicetree/bindings/sound/ |
| D | amlogic,axg-fifo.txt | 1 * Amlogic Audio FIFO controllers
12 - interrupts: interrupt specifier for the fifo.
13 - clocks: phandle to the fifo peripheral clock provided by the audio
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| /Documentation/devicetree/bindings/spi/ |
| D | spi_atmel.txt | 14 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
28 atmel,fifo-size = <32>;
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| /Documentation/devicetree/bindings/net/ieee802154/ |
| D | cc2520.txt | 10 - fifo-gpio: GPIO spec for the FIFO pin
27 fifo-gpio = <&gpio1 18 0>;
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| /Documentation/devicetree/bindings/serial/ |
| D | mvebu-uart.txt | 7 (32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
8 FIFO, baudrate limited to 230400).
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
11 accesses to the FIFO, baudrate unlimited by the dividers).
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| /Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 10 - fdd: FIFO DMA Request Delay
14 - fifo-th: DMA FIFO threshold
48 fifo-th = <0>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
17 and tx interrupt source per h/w fifo. Communication between different processors
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
23 instance. DRA7xx has multiple instances with different number of h/w fifo queues
55 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
83 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
84 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
90 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
97 associated with generating a tx/rx fifo interrupt.
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| /Documentation/admin-guide/blockdev/ |
| D | floppy.rst | 98 you have an FDC without a FIFO (8272A or 82072). 82072A and
100 If you use nodma mode, I suggest you also set the FIFO
104 If you have a FIFO-able FDC, the floppy driver automatically
113 Disables the FIFO entirely. This is needed if you get "Bus
118 Enables the FIFO. (default)
121 Sets the FIFO threshold. This is mostly relevant in DMA
129 To tune the fifo threshold, switch on over/underrun messages
132 messages, then the fifo threshold is too low. Try with a
136 fifo values without rebooting the machine for each test. Note
140 Usually, tuning the fifo threshold should not be needed, as
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| /Documentation/spi/ |
| D | pxa2xx.rst | 15 The driver is built around a "spi_message" fifo serviced by workqueue and a
16 tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
104 used to configure the SSP hardware fifo. These fields are critical to the
106 fifo overruns (especially in PIO mode transfers). Good default values are::
121 trailing bytes in the SSP receiver fifo. The correct value for this field is
169 .tx_threshold = 8, /* SSP hardward FIFO threshold */
170 .rx_threshold = 8, /* SSP hardward FIFO threshold */
177 .tx_threshold = 8, /* SSP hardward FIFO threshold */
178 .rx_threshold = 8, /* SSP hardward FIFO threshold */
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| /Documentation/devicetree/bindings/display/exynos/ |
| D | exynos7-decon.txt | 13 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
48 interrupt-names = "lcd_sys", "vsync", "fifo";
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-at91.txt | 18 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
56 atmel,fifo-size = <16>;
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