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/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Beniamin Bia <beniamin.bia@analog.com>
11 - Stefan Popa <stefan.popa@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
22 - adi,ad7605-4
23 - adi,ad7606-8
[all …]
/Documentation/devicetree/bindings/mfd/
Datmel-usart.txt4 - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
5 The compatible <chip> indicated will be the first SoC to support an
7 For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
8 - reg: Should contain registers location and length
9 - interrupts: Should contain interrupt
10 - clock-names: tuple listing input clock names.
12 - clocks: phandles to input clocks.
15 - #size-cells : Must be <0>
16 - #address-cells : Must be <1>
17 - cs-gpios: chipselects (internal cs not supported)
[all …]
Dmadera.txt1 Cirrus Logic Madera class audio codecs Multi-Functional Device
7 bindings/pinctrl/cirrus,madera-pinctrl.txt
8 bindings/regulator/arizona-regulator.txt
13 - compatible : One of the following chip-specific strings:
24 - reg : I2C slave address when connected using I2C, chip select number when
27 - DCVDD-supply : Power supply for the device as defined in
32 - AVDD-supply, DBVDD1-supply, DBVDD2-supply, CPVDD1-supply, CPVDD2-supply :
35 - DBVDD3-supply, DBVDD4-supply : Power supplies for the device
38 - SPKVDDL-supply, SPKVDDR-supply : Power supplies for the device
41 - SPKVDD-supply : Power supply for the device
[all …]
/Documentation/devicetree/bindings/w1/
Dw1-gpio.txt1 w1-gpio devicetree bindings
5 - compatible: "w1-gpio"
6 - gpios: one or two GPIO specs:
7 - the first one is used as data I/O pin
8 - the second one is optional. If specified, it is used as
13 - linux,open-drain: if specified, the data pin is considered in
14 open-drain mode.
21 compatible = "w1-gpio";
22 gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
/Documentation/devicetree/bindings/display/bridge/
Dthine,thc63lvd1024.txt2 -------------------------------------------
5 to parallel data outputs. The chip supports single/dual input/output modes,
8 Single or dual operation mode, output data mapping and DDR output modes are
12 - compatible: Shall be "thine,thc63lvd1024"
13 - vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
17 - powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
18 - oe-gpios: Output enable GPIO signal, pin name "OE". Active high
24 - port@0: First LVDS input port
25 - port@2: First digital CMOS/TTL parallel output
28 - port@1: Second LVDS input port
[all …]
Dti,sn65dsi86.txt2 --------------------------------
8 - compatible: Must be "ti,sn65dsi86"
9 - reg: i2c address of the chip, 0x2d as per datasheet
10 - enable-gpios: gpio specification for bridge_en pin (active high)
12 - vccio-supply: A 1.8V supply that powers up the digital IOs.
13 - vpll-supply: A 1.8V supply that powers up the displayport PLL.
14 - vcca-supply: A 1.2V supply that powers up the analog circuits.
15 - vcc-supply: A 1.2V supply that powers up the digital core.
18 - interrupts-extended: Specifier for the SN65DSI86 interrupt line.
20 - gpio-controller: Marks the device has a GPIO controller.
[all …]
Dsii902x.txt4 - compatible: "sil,sii9022"
5 - reg: i2c address of the bridge
8 - interrupts: describe the interrupt line used to inform the host
10 - reset-gpios: OF device-tree gpio specification for RST_N pin.
13 - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
16 - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
18 audio fifo. The first integer selects i2s audio pin for the
19 first audio fifo#0 (HDMI channels 1&2), second for fifo#1
21 pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
26 - clocks: phandle and clock specifier for each clock listed in
[all …]
/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
32 data rate mode operation. Refer notes below for the order of the cells and the
[all …]
Dfsl-imx-esdhc.txt7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
17 "fsl,imx6sx-usdhc"
18 "fsl,imx6ull-usdhc"
[all …]
/Documentation/devicetree/bindings/net/
Ddavicom-dm9000.txt4 - compatible = "davicom,dm9000";
5 - reg : physical addresses and sizes of registers, must contain 2 entries:
6 first entry : address register,
7 second entry : data register.
8 - interrupts : interrupt specifier specific to interrupt controller
11 - davicom,no-eeprom : Configuration EEPROM is not available
12 - davicom,ext-phy : Use external PHY
13 - reset-gpios : phandle of gpio that will be used to reset chip during probe
14 - vcc-supply : phandle of regulator that will be used to enable power to chip
21 interrupt-parent = <&gpn>;
[all …]
Dti-bluetooth.txt2 ---------------------------------
19 ../serial/slave-device.txt.
22 - compatible: should be one of the following:
24 "ti,wl1271-st"
25 "ti,wl1273-st"
26 "ti,wl1281-st"
27 "ti,wl1283-st"
28 "ti,wl1285-st"
29 "ti,wl1801-st"
30 "ti,wl1805-st"
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio.txt4 1) gpios property
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
15 cases should they contain more than one. If your device uses several GPIOs with
17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a parallel data line).
20 The exact purpose of each gpios property must be documented in the device tree
[all …]
Dwd,mbl-gpio.txt1 Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
3 The Western Digital MyBook Live has two memory-mapped GPIO controllers.
4 Both GPIO controller only have a single 8-bit data register, where GPIO
8 - compatible: should be "wd,mbl-gpio"
9 - reg-names: must contain
10 "dat" - data register
11 - reg: address + size pairs describing the GPIO register sets;
12 order must correspond with the order of entries in reg-names
13 - #gpio-cells: must be set to 2. The first cell is the pin number and
17 - gpio-controller: Marks the device node as a gpio controller.
[all …]
Dnvidia,tegra186-gpio.txt21 registers to do so. Code which simply wishes to read or write GPIO data does not
30 Tegra HW documentation describes a unified naming convention for all GPIOs
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
37 implemented GPIOs within each port varies. GPIO registers within a controller
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
49 represents the aggregate status for all GPIOs within a set of ports. Thus, the
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
[all …]
/Documentation/devicetree/bindings/display/
Dssd1307fb.txt4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,com-seq: Display uses sequential COM pin configuration
[all …]
/Documentation/driver-api/gpio/
Dlegacy.rst13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
18 which GPIOs. Drivers can be written generically, so that board setup code
19 passes such pin configuration data to drivers.
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
24 provide GPIOs; multifunction chips like power managers, and audio codecs
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
30 The exact capabilities of GPIOs vary between systems. Common options:
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
[all …]
Dconsumer.rst6 it describes the new descriptor-based interface. For a description of the
7 deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
10 Guidelines for GPIOs consumers
15 obtain and use GPIOs are available by including the following file:
23 - Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
27 - Truly optional GPIOLIB support - where the driver does not really make use
28 of the GPIOs on certain compile-time configurations for certain systems, but
29 will use it under other compile-time configurations. In this case the
33 All the functions that work with the descriptor-based GPIO interface are
40 Obtaining and Disposing GPIOs
[all …]
/Documentation/admin-guide/gpio/
Dsysfs.rst7 Documentation/ABI/obsolete/sysfs-gpio AND NEW USERSPACE CONSUMERS
16 ------------------------
18 configure a sysfs user interface to GPIOs. This is different from the
26 may need to temporarily remove that protection, first importing a GPIO,
27 then changing its output state, then updating the code before re-enabling
32 userspace GPIO can be used to determine system configuration data that
37 PLEASE READ THE DOCUMENT AT Documentation/driver-api/gpio/drivers-on-gpio.rst
41 --------------
44 - Control interfaces used to get userspace control over GPIOs;
46 - GPIOs themselves; and
[all …]
/Documentation/networking/caif/
Dspi_porting.txt1 - CAIF SPI porting -
3 - CAIF SPI basics:
6 Two extra GPIOs have been added in order to negotiate the transfers
8 CAIF over SPI is a SPI slave chip and two GPIOs (more details below).
12 - CAIF SPI framework:
15 two parts. The first part (called the interface part) deals with all
20 the physical hardware, both with regard to SPI and to GPIOs.
22 - Implementing a CAIF SPI device:
24 - Functionality provided by the CAIF SPI slave device:
34 a stream of data from the master. The xfer structure contains
[all …]
/Documentation/devicetree/bindings/sound/
Ddavinci-mcasp-audio.txt4 - compatible :
5 "ti,dm646x-mcasp-audio" : for DM646x platforms
6 "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms
7 "ti,am33xx-mcasp-audio" : for AM33xx platforms (AM33xx, AM43xx, TI81xx)
8 "ti,dra7-mcasp-audio" : for DRA7xx platforms
10 - reg : Should contain reg specifiers for the entries in the reg-names property.
11 - reg-names : Should contain:
13 existing software, it is recommended this is the first entry.
14 * "dat" for separate data port register access (optional).
15 - op-mode : I2S/DIT ops mode. 0 for I2S mode. 1 for DIT mode used for S/PDIF,
[all …]
/Documentation/firmware-guide/acpi/
Dgpio-properties.rst1 .. SPDX-License-Identifier: GPL-2.0
8 allows names to be given to GPIOs (and other things as well) returned
13 With _DSD we can now query GPIOs using a name instead of an integer
16 // Bluetooth device with reset and shutdown GPIOs
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () {"reset-gpios", Package() {^BTH, 1, 1, 0 }},
35 Package () {"shutdown-gpios", Package() {^BTH, 0, 0, 0 }},
58 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
61 It is possible to leave holes in the array of GPIOs. This is useful in
63 implemented as GPIOs and some as native signals. For example a SPI host
[all …]
Denumeration.rst1 .. SPDX-License-Identifier: GPL-2.0
13 that are accessed through memory-mapped registers.
15 In order to support this and re-use the existing drivers as much as
18 - Devices that have no bus connector resource are represented as
21 - Devices behind real busses where there is a connector resource
33 This means that when ACPI_HANDLE(dev) returns non-NULL the device was
35 device-specific configuration. There is an example of this below.
42 for the device and add supported ACPI IDs. If this same IP-block is used on
43 some other non-ACPI platform, the driver might work out of the box or needs
65 configuring GPIOs it can get its ACPI handle and extract this information
[all …]
/Documentation/devicetree/bindings/dma/
Dqcom_adm.txt4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
14 - clk
15 - c0
[all …]
/Documentation/driver-api/
Dsmsc_ece1099.rst5 What is smsc-ece1099?
6 ----------------------
8 The ECE1099 is a 40-Pin 3.3V Keyboard Scan Expansion
11 via the SMSC BC-Link interface or via the SMBus.
13 are multiplexed with GPIOs.
16 --------------------
26 of an interrupt, it should first read the Group Interrupt Status Register
34 ----------------------
36 - SMbus slave Interface
40 a computer host and its peripheral devices. The SMBus data
[all …]

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