Searched full:from (Results 1 – 25 of 2377) sorted by relevance
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| /Documentation/hwmon/ |
| D | ucd9200.rst | 29 [From datasheets] UCD9220, UCD9222, UCD9224, UCD9240, UCD9244, UCD9246, and
62 in1_input Measured voltage. From READ_VIN register.
63 in1_min Minimum Voltage. From VIN_UV_WARN_LIMIT register.
64 in1_max Maximum voltage. From VIN_OV_WARN_LIMIT register.
66 in1_crit Critical maximum voltage. From VIN_OV_FAULT_LIMIT
68 in1_min_alarm Voltage low alarm. From VIN_UV_WARNING status.
69 in1_max_alarm Voltage high alarm. From VIN_OV_WARNING status.
70 in1_lcrit_alarm Voltage critical low alarm. From VIN_UV_FAULT status.
71 in1_crit_alarm Voltage critical high alarm. From VIN_OV_FAULT status.
74 in[2-5]_input Measured voltage. From READ_VOUT register.
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| D | max8688.rst | 49 in1_input Measured voltage. From READ_VOUT register.
50 in1_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
51 in1_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
53 in1_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
55 in1_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
56 in1_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
57 in1_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
59 in1_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
65 curr1_input Measured current. From READ_IOUT register.
66 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
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| D | pmbus.rst | 179 supported, and determines available sensors from this information.
188 inX_input Measured voltage. From READ_VIN or READ_VOUT register.
190 From VIN_UV_WARN_LIMIT or VOUT_UV_WARN_LIMIT register.
192 From VIN_OV_WARN_LIMIT or VOUT_OV_WARN_LIMIT register.
194 From VIN_UV_FAULT_LIMIT or VOUT_UV_FAULT_LIMIT register.
196 From VIN_OV_FAULT_LIMIT or VOUT_OV_FAULT_LIMIT register.
197 inX_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
198 inX_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
200 From VOLTAGE_UV_FAULT status.
202 From VOLTAGE_OV_FAULT status.
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| D | f71882fg.rst | 10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
28 Datasheet: Available from the Fintek website
34 Addresses scanned: none, address read from Super I/O config space
36 Datasheet: Available from the Fintek website
42 Addresses scanned: none, address read from Super I/O config space
44 Datasheet: Available from the Fintek website
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
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| D | tps40422.rst | 48 in[1-2]_input Measured voltage. From READ_VOUT register.
51 curr[1-2]_input Measured current. From READ_IOUT register.
53 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
54 curr1_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT
56 curr1_max_alarm Current high alarm. From IOUT_OC_WARN_LIMIT status.
57 curr1_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status.
58 curr2_alarm Current high alarm. From IOUT_OC_WARNING status.
60 temp1_input Measured temperature. From READ_TEMPERATURE_2 register
62 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
63 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
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| D | ucd9000.rst | 26 From datasheets:
86 in[1-12]_input Measured voltage. From READ_VOUT register.
87 in[1-12]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
88 in[1-12]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
90 in[1-12]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
92 in[1-12]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
93 in[1-12]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
94 in[1-12]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
96 in[1-12]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
100 curr[1-12]_input Measured current. From READ_IOUT register.
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| D | max16064.rst | 49 in[1-4]_input Measured voltage. From READ_VOUT register.
50 in[1-4]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
51 in[1-4]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
53 in[1-4]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
55 in[1-4]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
56 in[1-4]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
57 in[1-4]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
59 in[1-4]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
64 temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
65 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
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| D | nct6775.rst | 15 Addresses scanned: ISA address retrieved from Super I/O registers
17 Datasheet: Available from the Nuvoton web site
23 Addresses scanned: ISA address retrieved from Super I/O registers
25 Datasheet: Available from Nuvoton upon request
31 Addresses scanned: ISA address retrieved from Super I/O registers
33 Datasheet: Available from Nuvoton upon request
39 Addresses scanned: ISA address retrieved from Super I/O registers
41 Datasheet: Available from Nuvoton upon request
47 Addresses scanned: ISA address retrieved from Super I/O registers
49 Datasheet: Available from Nuvoton upon request
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| D | lochnagar.rst | 31 power1_average_interval Power averaging time input valid from 1 to 1708mS
38 power2_average_interval Power averaging time input valid from 1 to 1708mS
45 power3_average_interval Power averaging time input valid from 1 to 1708mS
52 power4_average_interval Power averaging time input valid from 1 to 1708mS
59 power5_average_interval Power averaging time input valid from 1 to 1708mS
64 power6_average_interval Power averaging time input valid from 1 to 1708mS
71 power7_average_interval Power averaging time input valid from 1 to 1708mS
78 power8_average_interval Power averaging time input valid from 1 to 1708mS
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| /Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dp.txt | 15 For the Panel initialization, we read data from dp-controller node.
25 from common clock binding: handle to dp clock.
27 from common clock binding: Shall be "dp".
29 from general PHY binding: the phandle for the PHY device.
31 from general PHY binding: Should be "dp".
60 -interlaced: deprecated prop that can parsed from drm_display_mode.
61 -vsync-active-high: deprecated prop that can parsed from drm_display_mode.
62 -hsync-active-high: deprecated prop that can parsed from drm_display_mode.
63 -samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
64 -samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
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| /Documentation/scsi/ |
| D | ChangeLog.lpfc | 5 Changes from 20050323 to 20050413
11 * Merged patch from Christoph Hellwig <hch@lst.de>: split helpers
24 only be called from lpfc_sli_submit_iocb. Also make
47 Changes from 20050308 to 20050323
50 * Changed a few lines from patch submitted by Christoph Hellwig
53 * Merged patch from Christoph Hellwig (3/19): some misc patches
64 - don't call dma_sync function on allocations from
66 * Merged patch from Christoph Hellwig (3/19) - nlp_failMask isn't
73 * Merged patch from Christoph Hellwig (03/19) - fix initialization
74 order - scsi_add_host must happen last from scsi POV. Also some
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-etb10 | 5 Description: (RW) Add/remove a sink from a trace path. There can be multiple
17 value stored in this register+1 (from ARM ETB-TRM).
24 2. The value is read directly from HW register RDP, 0x004.
31 is read directly from HW register STS, 0x00C.
38 that is used to read entries from the Trace RAM over the APB
39 interface. The value is read directly from HW register RRP,
47 that is used to sets the write pointer to write entries from
49 from HW register RWP, 0x018.
56 read directly from HW register TRG, 0x01C.
63 is read directly from HW register CTL, 0x020.
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| D | sysfs-devices-power | 15 from sleep states, such as the memory sleep state (suspend to
20 used to activate the system from a sleep state. Such devices
33 be enabled to wake up the system from sleep states.
46 + "on\n" to prevent the device from being power managed;
51 from power managing the device at run time. Doing that while
87 the system from sleep states, this attribute is not present.
88 If the device is not enabled to wake up the system from sleep
99 system from sleep states, this attribute is not present. If
100 the device is not enabled to wake up the system from sleep
111 is not capable to wake up the system from sleep states, this
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| D | sysfs-bus-coresight-devices-tmc | 15 The value is read directly from HW register RSZ, 0x004.
22 is read directly from HW register STS, 0x00C.
29 that is used to read entries from the Trace RAM over the APB
30 interface. The value is read directly from HW register RRP,
38 that is used to sets the write pointer to write entries from
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
54 is read directly from HW register CTL, 0x020.
61 register. The value is read directly from HW register FFSR,
69 register. The value is read directly from HW register FFCR,
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| D | sysfs-bus-iio-light-isl29018 | 6 From ISL29018 Data Sheet (FN6619.4, Oct 8, 2012) regarding the
10 detection. The range of Scheme 0 proximity count is from 0 to
13 range of Scheme 1 proximity count is from -2^(n-1) to 2^(n-1).
18 0 Sensing IR from LED and ambient
19 1 Sensing IR from LED with ambient IR rejection
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| D | sysfs-devices-platform-ACPI-TAD | 14 BIT(4): Correct status reported for wakeups from S4/S5 if set
15 BIT(5): The AC timer wakes up from S4 if set
16 BIT(6): The AC timer wakes up from S5 if set
17 BIT(7): The DC timer wakes up from S4 if set
18 BIT(8): The DC timer wakes up from S5 if set
35 expires, it will immediately wake up the system from the S3
36 sleep state (and from S4/S5 too if supported) until its status
66 Bit(1): The timer has woken up the system from a sleep state
77 it will immediately wake up the system from the S3 sleep state
78 (and from S4/S5 too if supported) until its status is explicitly
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| /Documentation/admin-guide/ |
| D | numastat.rst | 10 numa_hit A process wanted to allocate memory from this node,
13 numa_miss A process wanted to allocate memory from another node,
14 but ended up with memory from this node.
17 but ended up with memory from another one.
19 local_node A process ran on this node and got memory from it.
21 other_node A process ran on this node and got memory from another node.
23 interleave_hit Interleaving wanted to allocate from this node
27 For easier reading you can use the numastat utility from the numactl package
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| /Documentation/devicetree/bindings/arm/ |
| D | sp810.txt | 14 - clock-names: from the common clock bindings, for more details see
18 - clocks: from the common clock bindings, phandle and clock
21 - #clock-cells: from the common clock bindings;
24 - clock-output-names: from the common clock bindings;
27 - assigned-clocks: from the common clock binding;
31 - assigned-clock-parents: from the common clock binding;
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| /Documentation/driver-api/ |
| D | device_link.rst | 59 or the device link needs to be added from a function which is guaranteed
60 not to run in parallel to a suspend/resume transition, such as from a
64 represents a driver presence dependency, yet is added from the consumer's
69 non-presence. [Note that it is valid to create a link from the consumer's
91 link is added from the consumer's ``->probe`` callback: ``DL_FLAG_RPM_ACTIVE``
92 can be specified to runtime resume the supplier and prevent it from suspending
97 Similarly, when the device link is added from supplier's ``->probe`` callback,
164 runtime PM integration is added from the busmaster device (consumer)
176 and an NHI device to manage the PCIe switch. On resume from system sleep,
181 device links from the hotplug ports (consumers) to the NHI device
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| /Documentation/vm/ |
| D | numa.rst | 9 This question can be answered from a couple of perspectives: the
12 From the hardware perspective, a NUMA system is a computer platform that
16 from the software abstraction thereof, we'll call the components/assemblies
25 cells at multiple distances from other cells.
29 to and accessible from any CPU attached to any cell and cache coherency
33 away the cell containing the CPU or IO bus making the memory access is from the
37 can have cells at multiple remote distances from any given cell.
87 from the same node before using remote nodes which are ordered by NUMA distance.
89 By default, Linux will attempt to satisfy memory allocation requests from the
91 Linux will attempt to allocate from the first node in the appropriate zonelist
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| /Documentation/devicetree/bindings/misc/ |
| D | atmel-ssc.txt | 21 - atmel,clk-from-rk-pin: bool property.
23 clock can get from TK pin, and also can get from RK pin. So, add
24 this parameter to choose where the clock from.
25 - By default the clock is from TK pin, if the clock from RK pin, this
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| /Documentation/devicetree/bindings/spi/ |
| D | nvidia,tegra114-spi.txt | 28 with this tap value. This property is used to tune the outgoing data from
30 Tap values vary based on the platform design trace lengths from Tegra SPI
31 to corresponding slave devices. Valid tap values are from 0 thru 63.
32 - nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
34 clock with respect to the data from the SPI slave device.
35 Tap values vary based on the platform design trace lengths from Tegra SPI
36 to corresponding slave devices. Valid tap values are from 0 thru 63.
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| /Documentation/media/v4l-drivers/ |
| D | imx.rst | 10 handles the flow of image frames to and from capture devices and
22 The IDMAC is the DMA controller for transfer of image frames to and from
48 captured frames from sensors directly to memory concurrently via four
58 motion). The deinterlaced output frames from the VDIC can be sent to the
97 defined that allow sending frames to the VDIC subdev directly from the
99 VDIC from memory buffers via a output/mem2mem devices.
112 the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has
115 stream from multiple virtual channels.
137 select from either camera sensors with a parallel interface, or from
138 MIPI CSI-2 virtual channels from imx6-mipi-csi2 entity. They have a
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| /Documentation/usb/ |
| D | ohci.rst | 8 from the "usb-ohci" driver from the 2.4 kernel series. The "usb-ohci" code
10 contributions from many others (read its copyright/licencing header).
14 compared to the earlier "Universal Host Controller Interface" (UHCI) from
16 from vendors other than Intel and VIA generally use OHCI.
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| /Documentation/infiniband/ |
| D | core_locking.rst | 15 are any methods from the list:
27 which may not sleep and must be callable from any context.
41 are therefore safe to call from any context.
48 the midlayer is also safe to call from any context.
71 A low-level driver must not perform a callback directly from the
74 handler directly from its post_send method. Instead, the low-level
93 return from CQ event handler
109 ib_unregister_device() from process context. It must not hold any
116 relating to a device before returning from the remove method.
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