Searched full:hart (Results 1 – 6 of 6) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
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| D | sifive,plic-1.0.0.txt | 7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
11 privilege modes per hart; machine mode and supervisor mode.
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 17 hart: A hardware execution context, which contains all the state
39 Identifies that the hart uses the RISC-V instruction set
40 and identifies the type of the hart.
51 hart. These values originate from the RISC-V Privileged
63 supported by the hart. These are documented in the RISC-V
145 // Example 2: Spike ISA Simulator with 1 Hart
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| /Documentation/timers/ |
| D | highres.rst | 64 Timers" was written by J. Stultz, D.V. Hart, & N. Aravamudan.
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| /Documentation/RCU/ |
| D | RTFP.txt | 1132 ,Author="Thomas E. Hart"
1270 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown"
1442 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown"
1911 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown and Jonathan Walpole"
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| /Documentation/media/v4l-drivers/ |
| D | bttv.rst | 1817 - HART Vision 848 (H-ART Vision 848)
1818 - HART Vision 878 (H-Art Vision 878)
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