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/Documentation/devicetree/bindings/arm/amlogic/
Damlogic,meson-gx-ao-secure.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
22 const: amlogic,meson-gx-ao-secure
24 - compatible
29 - const: amlogic,meson-gx-ao-secure
30 - const: syscon
35 amlogic,has-chip-id:
[all …]
/Documentation/hwmon/
Dsis5595.rst10 Addresses scanned: ISA in PCI-space encoded address
18 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
19 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
20 - Aurelien Jarno <aurelien@aurel32.net> 2.6 port
22 SiS southbridge has a LM78-like chip integrated on the same IC.
28 Version PCI ID PCI Revision
36 "blacklist" PCI ID and refuse to load.
39 NOT SUPPORTED PCI ID BLACKLIST PCI ID
55 -----------------
69 -----------
[all …]
Dlm90.rst18 Prefix: 'lm89' (no auto-detection)
54 http://www.onsemi.com/PowerSolutions/product.do?id=ADM1032
64 http://www.onsemi.com/PowerSolutions/product.do?id=ADT7461
74 http://www.onsemi.com/PowerSolutions/product.do?id=ADT7461A
84 http://www.onsemi.com/PowerSolutions/product.do?id=NCT1008
94 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497
104 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497
114 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500
124 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497
134 http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2578
[all …]
Dw83791d.rst10 Addresses scanned: I2C 0x2c - 0x2f
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/W83791D_W83791Gb.pdf
22 - Frodo Looijaard <frodol@dds.nl>,
23 - Philip Edelbrock <phil@netroedge.com>,
24 - Mark Studebaker <mdsxyz123@yahoo.com>
28 - Shane Huang (Winbond),
29 - Rudolf Marek <r.marek@assembler.cz>
33 - Sven Anders <anders@anduras.de>
34 - Marc Hulsman <m.hulsman@tudelft.nl>
37 -----------------
[all …]
/Documentation/devicetree/bindings/mips/
Dmscc.txt7 - compatible: "mscc,ocelot"
12 o CPU chip regs:
14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15 functionalities: chip ID, general purpose register for software use, reset
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
[all …]
/Documentation/devicetree/bindings/mtd/
Djedec,spi-nor.txt4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : May include a device-specific string consisting of the
7 manufacturer and name of the chip. A list of supported chip
9 Must also include "jedec,spi-nor" for any SPI NOR flash that can
10 be identified by the JEDEC READ ID opcode (0x9F).
12 Supported chip names:
50 The following chip names have been used historically to
52 JEDEC READ ID opcode (0x9F):
53 m25p05-nonjedec
54 m25p10-nonjedec
[all …]
Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
16 - #address-cells, #size-cells : Must be present if the device has
[all …]
/Documentation/devicetree/bindings/spi/
Dspi-sprd-adi.txt3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
8 ADI controller has 50 channels including 2 software read/write channels and
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
19 the analog chip address where user want to access by hardware components.
[all …]
/Documentation/w1/masters/
Dds2490.rst13 -----------
15 The Maxim/Dallas Semiconductor DS2490 is a chip
16 which allows to build USB <-> W1 bridges.
18 DS9490(R) is a USB <-> W1 bus master device
19 which has 0x81 family ID integrated chip and DS2490
20 low-level operational chip.
24 - The weak pullup current is a minimum of 0.9mA and maximum of 6.0mA.
25 - The 5V strong pullup is supported with a minimum of 5.9mA and a
27 - The hardware will detect when devices are attached to the bus on the
31 - The number of USB bus transactions could be reduced if w1_reset_send
[all …]
/Documentation/devicetree/bindings/fsi/
Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
[all …]
/Documentation/devicetree/bindings/mailbox/
Dti,message-manager.txt4 The Texas Instruments' Message Manager is a mailbox controller that has
5 configurable queues selectable at SoC(System on Chip) integration. The Message
7 "proxies" - each instance is unidirectional and is instantiated at SoC
13 --------------------
14 - compatible: Shall be: "ti,k2g-message-manager"
15 - reg-names queue_proxy_region - Map the queue proxy region.
16 queue_state_debug_region - Map the queue state debug
18 - reg: Contains the register map per reg-names.
19 - #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that
21 - interrupt-names: Contains interrupt names matching the rx transfer path
[all …]
Dti,secure-proxy.txt4 The Texas Instruments' secure proxy is a mailbox controller that has
5 configurable queues selectable at SoC(System on Chip) integration. The
7 called "threads" or "proxies" - each instance is unidirectional and is
14 --------------------
15 - compatible: Shall be "ti,am654-secure-proxy"
16 - reg-names target_data - Map the proxy data region
17 rt - Map the realtime status region
18 scfg - Map the configuration region
19 - reg: Contains the register map per reg-names.
20 - #mbox-cells Shall be 1 and shall refer to the transfer path
[all …]
/Documentation/i2c/muxes/
Di2c-mux-gpio.rst2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
22 | | | |---------------| |
23 ---------- ---------- - - - - -
[all …]
/Documentation/scsi/
Dncr53c8xx.txt5 95170 DEUIL LA BARRE - FRANCE
54 10.2.21 Suggest a default SCSI id for hosts
57 10.4 PCI configuration fix-up boot option
74 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
75 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
82 18.2 NCR chip in Big Endian mode of operations
88 The initial Linux ncr53c8xx driver has been a port of the ncr driver from
89 FreeBSD that has been achieved in November 1995 by:
92 The original driver has been written for 386bsd and FreeBSD by:
94 Stefan Esser <se@mi.Uni-Koeln.de>
[all …]
Dbnx2fc.txt17 eth0.1001-fcoe). Do not delete or disable these interfaces or FCoE operation
23 1. Ensure that fcoe-utils package is installed.
25 2. Configure the interfaces on which bnx2fc driver has to operate on.
28 b. copy cfg-ethx to cfg-eth5 if FCoE has to be enabled on eth5.
29 c. Repeat this for all the interfaces where FCoE has to be enabled.
30 d. Edit all the cfg-eth files to set "no" for DCB_REQUIRED** field, and
40 5. "Symbolic Name" in 'fcoeadm -i' output would display if bnx2fc has claimed
43 [root@bh2 ~]# fcoeadm -i
48 Driver: bnx2x 1.70.00-0
59 FC-ID (Port ID): 0x0F0377
[all …]
Daha152x.txt1 $Id: README.aha152x,v 1.2 1999/12/25 15:32:30 fischer Exp fischer $
2 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
4 Copyright 1993-1999 Jürgen Fischer <fischer@norbit.de>
9 bottom-half handler complete()).
11 The driver is much cleaner now, has support for the new
13 less polling loops), has slightly higher throughput (at
20 IRQ interrupt level (9-12; default 11)
21 SCSI_ID scsi id of controller (0-7; default 7)
31 -DAUTOCONF
32 use configuration the controller reports (AHA-152x only)
[all …]
/Documentation/devicetree/bindings/i2c/
Di2c-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wolfram@the-dreams.de>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - const: i2c-gpio
20 sda-gpios:
24 from <dt-bindings/gpio/gpio.h> since the signal is by definition
28 scl-gpios:
[all …]
/Documentation/firmware-guide/acpi/
Dgpio-properties.rst1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () {"reset-gpios", Package() {^BTH, 1, 1, 0 }},
35 Package () {"shutdown-gpios", Package() {^BTH, 0, 0, 0 }},
45 The device that has _CRS containing GpioIo()/GpioInt() resources,
58 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
62 cases like with SPI host controllers where some chip selects may be
64 controller can have chip selects 0 and 2 implemented as GPIOs and 1 as
68 "cs-gpios",
70 ^GPIO, 19, 0, 0, // chip select 0: GPIO
[all …]
/Documentation/admin-guide/perf/
Dhisi-pmu.rst5 The HiSilicon SoC chip includes various independent system device PMUs
12 called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
33 SCCL ID #3.
36 SCCL ID #1.
39 ID used to count the uncore PMU event.
[all …]
/Documentation/virt/kvm/devices/
Dmpic.txt15 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
20 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
23 must be 4-byte aligned.
28 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
32 For edge-triggered interrupts: Writing 1 is considered an activating
34 signaled edge has not been acknowledged, and 0 otherwise.
42 be instantiated. Once that device has been created, it's available as
43 irqchip id 0.
45 This irqchip 0 has 256 interrupt pins, which expose the interrupts in
48 The numbering is the same as the MPIC device tree binding -- based on
[all …]
/Documentation/devicetree/bindings/x86/
Dce4100.txt2 ---------------------------
5 format: <vendor>,<chip>-<device>.
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
34 - device_type
37 - reg
38 Local APIC ID, the unique number assigned to each processor by
42 ------------
44 This node describes the in-core peripherals. Required property:
[all …]
/Documentation/ABI/testing/
Dsysfs-kernel-irq8 but in a more machine-friendly format. This directory contains
15 Description: The IRQ action chain. A comma-separated list of zero or more
22 Description: Human-readable chip name supplied by the associated device
36 Description: Human-readable flow handler name as defined by the irq chip
43 Description: The number of times the interrupt has fired since boot. This
44 is a comma-separated list of counters; one per CPU in CPU id
/Documentation/media/uapi/v4l/
Dext-ctrls-flash.rst4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
10 .. _flash-controls:
24 .. _flash-controls-use-cases:
31 ------------------------------------------
42 ----------------------------------------
44 The synchronised LED flash is pre-programmed by the host (power and
53 ------------------
[all …]
/Documentation/sound/hd-audio/
Dnotes.rst2 More Notes on HD-Audio Driver
11 HD-audio is the new standard on-board audio component on modern PCs
12 after AC97. Although Linux has been supporting HD-audio since long
15 This document explains the brief trouble-shooting and debugging
16 methods for the HD-audio hardware.
18 The HD-audio component consists of two parts: the controller chip and
19 the codec chips on the HD-audio bus. Linux provides a single driver
20 for all controllers, snd-hda-intel. Although the driver name contains
21 a word of a well-known hardware vendor, it's not specific to it but for
22 all controller chips by other companies. Since the HD-audio
[all …]
/Documentation/sound/cards/
Dbt87x.rst19 does audio. snd-bt87x is a driver for the second function. It's a sound
22 into your sound card's line-in you probably don't need this driver if all
26 the chip, and some other cards use the audio function to transport MPEG
43 If you have an unknown card, please mail the ID and board name to
44 <alsa-devel@alsa-project.org>, regardless of whether audio capture works
51 The chip knows two different modes (digital/analog). snd-bt87x
73 The chip has three analog inputs. Consequently you'll get a mixer

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