| /Documentation/scsi/ |
| D | scsi-parameters.txt | 15 advansys= [HW,SCSI]
18 aha152x= [HW,SCSI]
21 aha1542= [HW,SCSI]
24 aic7xxx= [HW,SCSI]
27 aic79xx= [HW,SCSI]
30 atascsi= [HW,SCSI]
33 BusLogic= [HW,SCSI]
37 gdth= [HW,SCSI]
40 gvp11= [HW,SCSI]
42 ips= [HW,SCSI] Adaptec / IBM ServeRAID controller
[all …]
|
| /Documentation/devicetree/bindings/opp/ |
| D | qcom-nvmem-cpufreq.txt | 11 to provide the OPP framework with required information (existing HW bitmap).
45 - opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
150 opp-supported-hw = <0x77>;
156 opp-supported-hw = <0x70>;
162 opp-supported-hw = <0x7>;
168 opp-supported-hw = <0x70>;
174 opp-supported-hw = <0x7>;
180 opp-supported-hw = <0x70>;
186 opp-supported-hw = <0x7>;
192 opp-supported-hw = <0x70>;
[all …]
|
| /Documentation/networking/ |
| D | hinic.txt | 32 specific HW details about HW data structure formats.
34 hinic_hwdev - Implement the HW details of the device and include the components
40 HW Interface:
46 Configuration Status Registers Area that describes the HW Registers on the
60 card by AEQs. Also set the addresses of the IO CMDQs in HW.
75 used to set the QPs addresses in HW. The commands completion events are
79 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
84 HW device:
87 HW device - de/constructs the HW Interface, the MGMT components on the
98 Port Commands - Send commands to the HW device for port management
[all …]
|
| D | ieee802154.rst | 134 .. c:function:: void ieee802154_rx_irqsafe(struct ieee802154_hw *hw, struct sk_buff *skb, u8 lqi):
139 .. c:function:: void ieee802154_xmit_complete(struct ieee802154_hw *hw, struct sk_buff *skb, bool i…
149 int (*start)(struct ieee802154_hw *hw);
150 void (*stop)(struct ieee802154_hw *hw);
152 int (*xmit_async)(struct ieee802154_hw *hw, struct sk_buff *skb);
153 int (*ed)(struct ieee802154_hw *hw, u8 *level);
154 int (*set_channel)(struct ieee802154_hw *hw, u8 page, u8 channel);
158 .. c:function:: int start(struct ieee802154_hw *hw):
162 .. c:function:: void stop(struct ieee802154_hw *hw):
166 .. c:function:: int xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb):
[all …]
|
| /Documentation/watchdog/ |
| D | mlx-wdt.rst | 13 There are 2 types of HW watchdog implementations.
16 Actual HW timeout can be defined as a power of 2 msec.
22 Actual HW timeout is defined in sec. and it's the same as
27 Type 1 HW watchdog implementation exist in old systems and
28 all new systems have type 2 HW watchdog.
29 Two types of HW implementation have also different register map.
45 This mlx-wdt driver supports both HW watchdog implementations.
51 watchdog configuration flags: nowayout and start_at_boot, hw watchdog
56 Access to HW registers is performed through a generic regmap interface.
|
| /Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.txt | 4 this M4U have two generations of HW architecture. Generation one uses flat
42 As above, The Multimedia HW will go through SMI and M4U while it
43 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
45 HW should go though the m4u for translation or bypass it and talk
48 Normally we specify a local arbiter(larb) for each multimedia HW
51 video decode local arbiter, all these ports are according to the video HW.
59 "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
60 "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
62 generation one m4u HW.
63 "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
[all …]
|
| /Documentation/networking/dsa/ |
| D | lan9303.rst | 21 interfaces (which is the default state of a DSA device). Due to HW limitations,
22 no HW MAC learning takes place in this mode.
24 When both user ports are joined to the same bridge, the normal HW MAC learning
25 is enabled. This means that unicast traffic is forwarded in HW. Broadcast and
26 multicast is flooded in HW. STP is also supported in this mode. The driver
37 - The HW does not support VLAN-specific fdb entries
|
| /Documentation/driver-api/iio/ |
| D | hw-consumer.rst | 2 HW consumer
6 The Industrial I/O HW consumer offers a way to bond these IIO devices without
8 :file:`drivers/iio/buffer/hw-consumer.c`
18 HW consumer setup
22 A typical IIO HW consumer setup looks like this::
48 .. kernel-doc:: drivers/iio/buffer/industrialio-hw-consumer.c
|
| /Documentation/devicetree/bindings/cpufreq/ |
| D | ti-cpufreq.txt | 25 - opp-supported-hw: Two bitfields indicating:
69 opp-supported-hw = <0x06 0x0010>;
76 opp-supported-hw = <0x01 0x00FF>;
83 opp-supported-hw = <0x06 0x0020>;
90 opp-supported-hw = <0x01 0xFFFF>;
96 opp-supported-hw = <0x06 0x0040>;
102 opp-supported-hw = <0x01 0xFFFF>;
108 opp-supported-hw = <0x06 0x0080>;
114 opp-supported-hw = <0x01 0xFFFF>;
120 opp-supported-hw = <0x06 0x0100>;
[all …]
|
| D | imx-cpufreq-dt.txt | 6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
12 - opp-supported-hw: Two bitmaps indicating:
28 opp-supported-hw = <0xf>, <0x3>;
35 opp-supported-hw = <0xe>, <0x7>;
|
| /Documentation/driver-api/ |
| D | clk.rst | 51 struct clk_hw *hw;
70 int (*prepare)(struct clk_hw *hw);
71 void (*unprepare)(struct clk_hw *hw);
72 int (*is_prepared)(struct clk_hw *hw);
73 void (*unprepare_unused)(struct clk_hw *hw);
74 int (*enable)(struct clk_hw *hw);
75 void (*disable)(struct clk_hw *hw);
76 int (*is_enabled)(struct clk_hw *hw);
77 void (*disable_unused)(struct clk_hw *hw);
78 unsigned long (*recalc_rate)(struct clk_hw *hw,
[all …]
|
| D | ntb.rst | 174 * *debugfs*/ntb\_tool/*hw*/
176 NTB device probed by the tool. This directory is shortened to *hw*
178 * *hw*/db
184 * *hw*/mask
187 * *hw*/peer\_db
190 * *hw*/peer\_mask
193 * *hw*/spad
199 * *hw*/peer\_spad
210 * *debugfs*/ntb\_tool/*hw*/
212 NTB device probed by the tool. This directory is shortened to *hw*
[all …]
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-etb10 | 24 2. The value is read directly from HW register RDP, 0x004.
31 is read directly from HW register STS, 0x00C.
39 interface. The value is read directly from HW register RRP,
49 from HW register RWP, 0x018.
56 read directly from HW register TRG, 0x01C.
63 is read directly from HW register CTL, 0x020.
70 register. The value is read directly from HW register FFSR,
78 register. The value is read directly from HW register FFCR,
|
| D | sysfs-bus-coresight-devices-tmc | 15 The value is read directly from HW register RSZ, 0x004.
22 is read directly from HW register STS, 0x00C.
30 interface. The value is read directly from HW register RRP,
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
54 is read directly from HW register CTL, 0x020.
61 register. The value is read directly from HW register FFSR,
69 register. The value is read directly from HW register FFCR,
|
| D | sysfs-bus-coresight-devices-etm4x | 290 The value it taken directly from the HW.
297 (0x310). The value is taken directly from the HW.
304 (0x314). The value is taken directly from the HW.
311 (0xFB4). The value is taken directly from the HW.
318 (0xFB8). The value is taken directly from the HW.
325 (0xFC8). The value is taken directly from the HW.
332 (0xFCC). The value is taken directly from the HW.
339 (0xFE0). The value is taken directly from the HW.
346 (0xFE4). The value is taken directly from the HW.
353 (0xFE8). The value is taken directly from the HW.
[all …]
|
| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 47 - hw-caps-read-idle-ctrl: Have this property if the controller
50 - hw-caps-dll-calib-ctrl: Have this property if the controller
53 - hw-caps-ll-interface : Have this property if the controller
56 - hw-caps-temp-alert : Have this property if the controller
67 hw-caps-read-idle-ctrl;
68 hw-caps-ll-interface;
69 hw-caps-temp-alert;
|
| /Documentation/devicetree/bindings/clock/ti/ |
| D | interface.txt | 19 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
21 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
22 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
23 "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
24 "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.txt | 5 Mediatek SMI have two generations of HW architecture, here is the list
27 - clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
28 for generation 2 smi HW as follows:
34 clock domain, this clock is only needed by generation 1 smi HW.
35 and these 2 option clocks for generation 2 smi HW:
|
| /Documentation/devicetree/bindings/thermal/ |
| D | rockchip-thermal.txt | 30 - rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
31 - rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
32 - rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
50 rockchip,hw-tshut-temp = <95000>;
51 rockchip,hw-tshut-mode = <0>;
52 rockchip,hw-tshut-polarity = <0>;
|
| /Documentation/devicetree/bindings/dma/ |
| D | qcom_hidma_mgmt.txt | 7 Each HIDMA HW instance consists of multiple DMA channels. These channels
37 Once a reset is applied to the HW, HW starts a timer for reset operation
38 to confirm. If reset is not completed within this time, HW reports reset
50 - compatible: must contain "qcom,hidma-1.0" for initial HW or
51 "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
|
| /Documentation/sound/cards/ |
| D | audiophile-usb.rst | 127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
135 One exception is the hw:1,2 port which was reported to be Little Endian
137 This has been fixed in kernel 2.6.23 and above and now the hw:1,2 interface
144 % aplay -D hw:1,0 -c2 -t raw -r48000 -fS24_3BE test.raw
148 % arecord -D hw:1,1 -c2 -t raw -r48000 -fS24_3BE test.raw
152 % aplay -D hw:1,1 -c2 -t raw -r48000 -fS16_BE test.raw
156 % aplay -D hw:1,2 --channels=6 ac3_S16_BE_encoded_file.raw
199 - hw:1,0 is not available in capture mode
[all …]
|
| /Documentation/virt/kvm/devices/ |
| D | xive.txt | 18 The KVM device exposes different MMIO ranges of the XIVE HW which
49 interrupts are from a different HW controller (PHB4) and the ESB
53 kvmppc_xive_clr_mapped() are called when the device HW irqs are
57 The handler will insert the ESB page corresponding to the HW
94 -ENXIO: Could not allocate underlying HW interrupt
114 underlying HW interrupt failed
149 -EIO: Configuration of the underlying HW failed
162 called the NVT. When a VP is not dispatched on a HW processor
163 thread, this structure can be updated by HW if the VP is the target
|
| /Documentation/devicetree/bindings/reset/ |
| D | reset.txt | 21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
|
| /Documentation/devicetree/bindings/watchdog/ |
| D | alphascale-asm9260.txt | 19 "hw" - hw reset (default).
34 alphascale,mode = "hw";
|
| /Documentation/devicetree/bindings/mmc/ |
| D | uniphier-sd.txt | 14 "hw" - should exist if eMMC hw reset line is available
33 - cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt
|