Searched full:idle (Results 1 – 25 of 183) sorted by relevance
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 8 CPU Idle Time Management
21 memory or executed. Those states are the *idle* states of the processor.
23 Since part of the processor hardware is not used in idle states, entering them
27 CPU idle time management is an energy-efficiency feature concerned about using
28 the idle states of processors for this purpose.
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
44 enter an idle state, that applies to the processor as a whole.
52 enter an idle state, that applies to the core that asked for it in the first
56 except for one have been put into idle states at the "core level" and the
57 remaining core asks the processor to enter an idle state, that may trigger it
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| D | strategies.rst | 32 ``inactive`` (idle). If they are active, they have to be in power states
40 as a whole is regarded as "runtime idle" which may be very close to a sleep
46 runtime idle in one go. For this reason, systems usually use less energy in
47 sleep states than when they are runtime idle most of the time.
54 use the working-state power management in case it becomes idle, because the user
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 5 idle states. The description of these idle states is exposed via the
10 Typically each idle state has the following associated properties:
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
16 idle states and so on. The flag bits are as follows:
19 CPU from idle to running.
22 this idle state in order to accrue power-savings
27 The following properties provide details about the idle states. These
29 provides the value of that property for the idle state associated with
32 If idle-states are defined, then the properties
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| /Documentation/devicetree/bindings/arm/ |
| D | idle-states.txt | 2 ARM idle states binding description
12 the range of dynamic idle states that a processor can enter at run-time, can be
14 to enter/exit specific idle states on a given processor.
27 PM implementation to put the processor in different idle states (which include
28 states listed above; "off" state is not an idle state since it does not have
31 Idle state parameters (e.g. entry latency) are platform specific and need to be
35 The device tree binding definition for ARM idle states is the subject of this
39 2 - idle-states definitions
42 Idle states are characterized for a specific system through a set of
44 triggered upon idle states entry and exit.
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| /Documentation/driver-api/thermal/ |
| D | intel_powerclamp.rst | 15 - Idle Injection
44 idle injection across all online CPU threads was introduced. The goal
55 Idle Injection
68 If the kernel can also inject idle time to the system, then a
71 control system, where the target set point is a user-selected idle
73 between the actual package level C-state residency ratio and the target idle
81 thread synchronizes its idle time and duration, based on the rounding
89 Alignment of idle time around jiffies ensures scalability for HZ
92 kidle_inject/cpu. During idle injection, it runs monitor/mwait idle
96 The NOHZ schedule tick is disabled during idle time, but interrupts
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 1 QCOM Idle States for cpuidle driver
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
34 between the time it enters idle and the next known wake up. SPC mode is used
37 sequence for this idle state is programmed to power down the supply to the
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 10 CPU Idle Time Management
18 CPU Idle Time Management Subsystem
23 cores) is idle after an interrupt or equivalent wakeup event, which means that
24 there are no tasks to run on it except for the special "idle" task associated
26 belongs to. That can be done by making the idle logical CPU stop fetching
28 depended on by it into an idle state in which they will draw less power.
30 However, there may be multiple different idle states that can be used in such a
33 particular idle state. That is the role of the CPU idle time management
40 units: *governors* responsible for selecting idle states to ask the processor
45 CPU Idle Time Governors
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| /Documentation/admin-guide/mm/ |
| D | idle_page_tracking.rst | 4 Idle Page Tracking
10 The idle page tracking feature allows to track which memory pages are being
11 accessed by a workload and which are idle. This information can be useful for
23 The idle page tracking API is located at ``/sys/kernel/mm/page_idle``.
30 set, the corresponding page is idle.
32 A page is considered idle if it has not been accessed since it was marked idle
35 To mark a page idle one has to set the bit corresponding to
41 page types (e.g. SLAB pages) an attempt to mark a page idle is silently ignored,
42 and hence such pages are never reported idle.
44 For huge pages the idle flag is set only on the head page, so one has to read
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.txt | 1 PM Domain Idle State Node:
3 A domain idle state node represents the state parameters that will be used to
11 Definition: Must be "domain-idle-state".
17 microseconds required to enter the idle state.
25 in microseconds required to exit the idle state.
31 in microseconds after which the idle state will yield
33 i the idle state.
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| D | power_domain.txt | 32 - domain-idle-states : A phandle of an idle-state that shall be soaked into a
33 generic domain power state. The idle state definitions are
34 compatible with domain-idle-state specified in [1]. phandles
35 that are not compatible with domain-idle-state will be
37 The domain-idle-state property reflects the idle state of this PM domain and
38 not the idle states of the devices or sub-domains in the PM domain. Devices
39 and sub-domains have their own idle-states independent of the parent
40 domain's idle states. In the absence of this property, the domain would be
84 domain-idle-states = <&DOMAIN_RET>, <&DOMAIN_PWR_DN>;
92 domain-idle-states = <&DOMAIN_PWR_DN>;
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| /Documentation/timers/ |
| D | no_hz.rst | 19 2. Omit scheduling-clock ticks on idle CPUs (CONFIG_NO_HZ_IDLE=y or
23 3. Omit scheduling-clock ticks on CPUs that are either idle or that
40 that use short bursts of CPU, where there are very frequent idle
41 periods, but where these idle periods are also quite short (tens or
46 other than increasing the overhead of switching to and from idle and
52 However, if you are instead running a light workload with long idle
65 Omit Scheduling-Clock Ticks For Idle CPUs
68 If a CPU is idle, there is little point in sending it a scheduling-clock
71 and an idle CPU has no duties to shift its attention among.
74 scheduling-clock interrupts to idle CPUs, which is critically important
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| /Documentation/scheduler/ |
| D | sched-stats.rst | 50 4) # of times schedule() left the processor idle
76 of idleness (idle, busy, and newly idle):
79 cpu was idle
81 the load did not require balancing when the cpu was idle
83 more tasks and failed, when the cpu was idle
85 load_balance() in this domain when the cpu was idle
87 was idle
89 the target task was cache-hot when idle
91 not find a busier queue while the cpu was idle
93 cpu was idle but no busier group was found
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| D | sched-arch.rst | 22 CPU idle
26 1. Preempt should now disabled over idle routines. Should only
30 be cleared until the running task has called schedule(). Idle
51 5. TIF_POLLING_NRFLAG can be set by idle routines that do not
63 sleeping idle functions.
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-pinctrl.txt | 39 The only exception is that no bus will be created for a state named "idle". If
43 pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
44 pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
45 pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
50 If an idle state is defined, whenever an access is not being made to a device
51 on a child bus, the idle pinctrl state will be programmed into hardware.
53 If an idle state is not defined, the most recently used pinctrl state will be
66 pinctrl-names = "ddc", "pta", "idle";
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| D | i2c-mux-reg.txt | 23 - idle-state: value to set the muxer to when idle. When no value is
29 If an idle state is defined, using the idle-state (optional) property,
31 register will be set according to the idle value.
33 If an idle state is not defined, the most recently used value will be
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| D | i2c-mux-gpio.txt | 29 - idle-state: value to set the muxer to when idle. When no value is
39 If an idle state is defined, using the idle-state (optional) property,
41 GPIOs will be set according to the idle value.
43 If an idle state is not defined, the most recently used value will be
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| /Documentation/devicetree/bindings/mfd/ |
| D | twl4030-power.txt | 11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
17 When using ti,twl4030-power-idle, the TI recommended configuration
18 for idle modes is loaded to the tlw4030 PMIC.
20 When using ti,twl4030-power-idle-osc-off, the TI recommended
22 down during off-idle. Note that this does not work on all boards
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| /Documentation/devicetree/bindings/watchdog/ |
| D | atmel-sama5d4-wdt.txt | 15 - atmel,idle-halt: present if you want to stop the watchdog when the CPU is
16 in idle state.
18 watchdog not counting when the CPU is in idle state, therefore the
20 if the CPU stop working while it is in idle state, which is probably
33 atmel,idle-halt;
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| D | atmel-wdt.txt | 28 - atmel,idle-halt : Should be present if you want to stop the watchdog when
29 entering idle state.
31 watchdog not counting when the CPU is in idle state, therefore the
33 if the CPU stop working while it is in idle state, which is probably
48 atmel,idle-halt;
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| /Documentation/devicetree/bindings/mux/ |
| D | mux-controller.txt | 127 have when it is idle. The idle-state property is used for this. If the
128 idle-state is not present, the mux controller is typically left as is when
129 it is idle. For multiplexer chips that expose several mux controllers, the
130 idle-state property is an array with one idle state for each mux controller.
133 as is when it is idle. This is the default, but can still be useful for
135 there is a need to "step past" a mux controller and set some other idle
139 multiplexer. Using this disconnected high-impedance state as the idle state
140 is indicated with idle state (-2).
156 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
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| D | adi,adg792a.txt | 18 - idle-state : if present, array of states that the mux controllers will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
37 idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>;
63 idle-state = <1>;
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| D | adi,adgs1408.txt | 18 - idle-state : if present, the state that the mux controller will have
19 when idle. The special state MUX_IDLE_AS_IS is the default and
29 * Mux state set to idle as is (no idle-state declared)
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| /Documentation/trace/ |
| D | events-nmi.rst | 41 …<idle>-0 [000] d.h3 505.397558: nmi_handler: perf_event_nmi_handler() delta_ns: 3236765 hand…
42 …<idle>-0 [000] d.h3 505.805893: nmi_handler: perf_event_nmi_handler() delta_ns: 3174234 hand…
43 …<idle>-0 [000] d.h3 506.158206: nmi_handler: perf_event_nmi_handler() delta_ns: 3084642 hand…
44 …<idle>-0 [000] d.h3 506.334346: nmi_handler: perf_event_nmi_handler() delta_ns: 3080351 hand…
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| D | ftrace.rst | 1080 <idle>-0 [001] dNs4 21169.031481: wake_up_idle_cpu <-add_timer_on
1081 <idle>-0 [001] dNs4 21169.031482: _raw_spin_unlock_irqrestore <-add_timer_on
1082 <idle>-0 [001] .Ns4 21169.031484: sub_preempt_count <-_raw_spin_unlock_irqrestore
1084 <idle>-0 [002] .N.1 21169.031484: rcu_idle_exit <-cpu_idle
1085 <idle>-0 [001] .Ns3 21169.031484: _raw_spin_unlock <-clocksource_watchdog
1086 <idle>-0 [001] .Ns3 21169.031485: sub_preempt_count <-_raw_spin_unlock
1157 <idle>-0 [002] 23636.756054: ttwu_do_activate.constprop.89 <-try_to_wake_up
1158 <idle>-0 [002] 23636.756054: activate_task <-ttwu_do_activate.constprop.89
1159 <idle>-0 [002] 23636.756055: enqueue_task <-activate_task
1334 <idle>-0 0d.s2 0us+: _raw_spin_lock_irq <-run_timer_softirq
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| /Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 31 power-down idle period in which memories are
32 placed into power-down mode if bus is idle
36 self-refresh idle period in which memories are
37 placed into self-refresh mode if bus is idle
43 clock gating idle period. Memories are placed
45 clock arg gating started if bus is idle for
48 - rockchip,srpd_lite_idle : Defines the self-refresh power down idle
50 self-refresh power down mode if bus is idle
54 - rockchip,standby_idle : Defines the standby idle period in which
57 be gated if bus is idle for standby_idle * DFI
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