Searched full:internal (Results 1 – 25 of 680) sorted by relevance
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| /Documentation/driver-api/ |
| D | basics.rst | 8 :internal:
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| D | w1.rst | 7 W1 API internal to the kernel
10 W1 API internal to the kernel
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27 :internal:
40 W1 internal initialization for master devices.
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48 W1 internal initialization for master devices.
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| D | infrastructure.rst | 8 :internal:
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| D | input.rst | 8 :internal:
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| /Documentation/devicetree/bindings/sound/ |
| D | img,pistachio-internal-dac.txt | 1 Pistachio internal DAC DT bindings
5 - compatible: "img,pistachio-internal-dac"
8 node which contains the internal dac control registers
14 internal_dac: internal-dac {
15 compatible = "img,pistachio-internal-dac";
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| D | mvebu-audio.txt | 19 The first one is mandatory and defines the internal clock.
23 "internal" for the internal clock
33 clock-names = "internal";
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| D | renesas,fsi.txt | 15 - fsia,use-internal-clock : FSI uses internal clock when master mode.
19 - fsib,use-internal-clock : same as fsia
30 fsia,use-internal-clock;
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| D | nvidia,tegra-audio-rt5677.txt | 21 * Internal Mic 1
22 * Internal Mic 2
48 "DMIC L1", "Internal Mic 1",
49 "DMIC R1", "Internal Mic 1",
50 "DMIC L2", "Internal Mic 2",
51 "DMIC R2", "Internal Mic 2",
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| D | samsung-i2s.txt | 8 secondary fifo, s/w reset control and internal mux for root clk src.
10 playback, stereo channel capture, secondary fifo using internal
11 or external dma, s/w reset control, internal mux for root clk src
28 i2s0 uses some base clocks from CMU and some are from audio subsystem internal
34 clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
59 - samsung,idma-addr: Internal DMA register base address of the audio
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| /Documentation/networking/ |
| D | kapi.rst | 12 :internal:
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cdns,xtensa-pic.txt | 8 When it's 1, the first cell is the internal IRQ number.
10 specifies whether it's internal (0) or external (1).
12 core variants it may be mapped to different internal IRQ.
19 /* one cell: internal irq number,
20 * two cells: second cell == 0: internal irq number
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
50 adi,rx-internal-delay-ps = <1800>;
51 adi,tx-internal-delay-ps = <2200>;
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| D | qcom-emac.txt | 4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
16 - internal-phy : phandle to the internal PHY node
19 Internal PHY node:
46 internal-phy = <&emac_sgmii>;
95 internal-phy = <&emac_sgmii>;
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| D | ti,dp83867.txt | 5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
18 internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
19 should use "rgmii-id" if internal delays are desired as this may be
56 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
57 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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| D | marvell-neta-bm.txt | 8 - internal-mem: a phandle to BM internal SRAM definition.
33 internal-mem = <&bm_bppi>;
38 - internal SRAM node:
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| /Documentation/devicetree/bindings/mmc/ |
| D | amlogic,meson-gx.txt | 19 "clkin0" - Parent clock of internal mux
20 "clkin1" - Other parent clock of internal mux
21 The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
23 - resets : phandle of the internal reset line
26 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 8 0 = tclk (Internal Bus clock)
15 0 = tclk (Internal Bus clock)
21 0 = tclk (Internal Bus clock)
27 0 = tclk (Internal Bus clock)
30 3 = hclk (SDRAM Controller Internal Clock)
35 0 = tclk (Internal Bus clock)
41 0 = tclk (Internal Bus clock)
47 0 = tclk (Internal Bus clock)
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| /Documentation/core-api/ |
| D | kernel-api.rst | 10 :internal:
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| D | tracepoint.rst | 37 :internal:
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| /Documentation/admin-guide/ |
| D | rapidio.rst | 46 :internal:
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,drif.txt | 14 As per datasheet, each DRIF channel (drifn) is made up of two internal
15 channels (drifn0 & drifn1). These two internal channels share the common
16 CLK & SYNC. Each internal channel has its own dedicated resources like
17 irq, dma channels, address space & clock. This internal split is not
20 The device tree model represents each internal channel as a separate node.
21 The internal channels sharing the CLK & SYNC are tied together by their
24 internal channel.
26 When both internal channels are enabled they need to be managed together
29 properties of both the internal channels. This channel is identified by a
33 - When both the internal channels that are bonded together are enabled,
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| /Documentation/xtensa/ |
| D | atomctl.rst | 17 0x28: (WB: Internal, WT: Internal, BY:Exception)
27 support the Internal Operation.
49 2 Internal Operation Internal Operation Reserved
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| /Documentation/ABI/testing/ |
| D | debugfs-driver-genwqe | 15 Description: Internal chip state of UID0 (unit id 0).
21 Description: Internal chip state of UID1.
27 Description: Internal chip state of UID2.
40 Description: Internal chip state of UID0 before card was reset.
46 Description: Internal chip state of UID1 before card was reset.
52 Description: Internal chip state of UID2 before card was reset.
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| /Documentation/gpu/ |
| D | i915.rst | 23 :internal:
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| D | drm-kms-helpers.rst | 7 userspace requests to kernel internal objects. Everything else is handled by a
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