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/Documentation/devicetree/bindings/arm/
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
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/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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Dbrcm,bcm7038-l1-intc.txt1 Broadcom BCM7038-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
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Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
22 2-4 status words to determine which IRQs are pending
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/Documentation/ia64/
Dirq-redir.rst2 IRQ affinity on IA64 platforms
8 By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
10 that described in Documentation/IRQ-affinity.txt for i386 systems.
14 CPUs. Only the first non-zero bit is taken into account.
21 first non-zero bit is the selected CPU. This format has been kept for
24 Set the delivery mode of interrupt 41 to fixed and route the
38 gives the target CPU mask for the specified interrupt vector. If the CPU
39 mask is preceded by the character "r", the interrupt is redirectable
49 IO-SAPIC interrupts are initialized with CPU#0 as their default target
55 - minimal for an idle task,
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/Documentation/virt/kvm/devices/
Darm-vgic-v3.txt1 ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)
6 KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
9 will act as the VM interrupt controller, requiring emulated user-space devices
19 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
24 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
31 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
33 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
35 - index encodes the unique redistributor region index
36 - flags: reserved for future use, currently 0
37 - base field encodes bits [51:16] of the guest physical base address
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/Documentation/networking/
Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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Dpktgen.txt4 ------------------------------------
6 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
8 running, pktgen creates a thread for each CPU with affinity to that CPU.
29 overload type of benchmarking, as this could hurt the normal use-case.
32 # ethtool -G ethX tx 1024
41 ring-buffers for various performance reasons, and packets stalling
46 and the cleanup interval is affected by the ethtool --coalesce setting
47 of parameter "rx-usecs".
50 # ethtool -C ethX rx-usecs 30
55 Pktgen creates a thread for each CPU with affinity to that CPU.
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Dx25-iface.txt21 -----------------------------
45 -----------------------------
71 (Henner Eisen, 2000-10-28)
77 - With Linux 2.4.x (and above) SMP kernels, packet ordering is not
81 - Data passed upstream by means of netif_rx() might be dropped by the
86 handle such N-Reset events gracefully. And frequent N-Reset events
91 SMP re-ordering will not occur if the driver's interrupt handler is
94 - Driver authors should use irq affinity for the interrupt handler.
104 automatically cause the peer to re-transmit the dropped packet
122 The driver could uses this for flow-controlling the peer by means
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
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/Documentation/networking/device_drivers/freescale/
Ddpaa.txt11 - DPAA Ethernet Overview
12 - DPAA Ethernet Supported SoCs
13 - Configuring DPAA Ethernet in your kernel
14 - DPAA Ethernet Frame Processing
15 - DPAA Ethernet Features
16 - DPAA IRQ Affinity and Receive Side Scaling
17 - Debugging
30 - Peripheral Access Memory Unit (PAMU) (* needed only for PPC platforms)
32 - Frame Manager (FMan)
34 - Queue Manager (QMan), Buffer Manager (BMan)
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/Documentation/admin-guide/hw-vuln/
Dl1tf.rst1 L1TF - L1 Terminal Fault
10 -------------------
15 - Processors from AMD, Centaur and other non Intel vendors
17 - Older processor models, where the CPU family is < 6
19 - A range of Intel ATOM processors (Cedarview, Cloverview, Lincroft,
22 - The Intel XEON PHI family
24 - Intel processors which have the ARCH_CAP_RDCL_NO bit set in the
33 ------------
38 CVE-2018-3615 L1 Terminal Fault SGX related aspects
39 CVE-2018-3620 L1 Terminal Fault OS, SMM related aspects
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/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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/Documentation/ABI/stable/
Dsysfs-driver-ib_srp1 What: /sys/class/infiniband_srp/srp-<hca>-<port_number>/add_target
4 Contact: linux-rdma@vger.kernel.org
7 a comma-separated list of login parameters to this sysfs
9 * id_ext, a 16-digit hexadecimal number specifying the eight
10 byte identifier extension in the 16-byte SRP target port
13 * ioc_guid, a 16-digit hexadecimal number specifying the eight
14 byte I/O controller GUID portion of the 16-byte target port
16 * dgid, a 32-digit hexadecimal number specifying the
18 * pkey, a four-digit hexadecimal number specifying the
20 * service_id, a 16-digit hexadecimal number specifying the
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Dsysfs-class-infiniband2 -------------------------------------------------
9 Contact: linux-rdma@vger.kernel.org
22 Contact: linux-rdma@vger.kernel.org
32 Contact: linux-rdma@vger.kernel.org
37 What: /sys/class/infiniband/<device>/ports/<port-num>/lid
38 What: /sys/class/infiniband/<device>/ports/<port-num>/rate
39 What: /sys/class/infiniband/<device>/ports/<port-num>/lid_mask_count
40 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_sl
41 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_lid
42 What: /sys/class/infiniband/<device>/ports/<port-num>/state
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/Documentation/arm64/
Dacpi_object_usage.rst16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IORT,
24 - Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IBFT, IVRS, LPIT,
47 Optional, not currently supported, with no real use-case for an
55 time as ARM-compatible hardware is available, and the specification
123 UEFI-based; if it is UEFI-based, this table may be supplied. When this
139 the hardware reduced profile, and only 64-bit address fields will
156 filled in properly - that the PSCI_COMPLIANT flag is set and that
157 PSCI_USE_HVC is set or unset as needed (see table 5-37).
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/Documentation/networking/device_drivers/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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Dixgbe.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Known Issues
17 - Support
36 ----------------------------------
38 82599-BASED ADAPTERS
41 - If your 82599-based Intel(R) Network Adapter came with Intel optics or is an
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/Documentation/admin-guide/
Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
56 Documentation/firmware-guide/acpi/debug.rst for more information about
61 Enable PCI/PCI interrupt routing info messages:
119 Disable auto-serialization of AML methods
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/Documentation/RCU/
DwhatisRCU.txt1 What is RCU? -- "Read, Copy, Update"
18 during the 2.5 development effort that is optimized for read-mostly
32 6. ANALOGY WITH READER-WRITER LOCKING
48 everything, feel free to read the whole thing -- but if you are really
50 never need this document anyway. ;-)
82 b. Wait for all previous readers to complete their RCU read-side
91 use much lighter-weight synchronization, in some cases, absolutely no
92 synchronization at all. In contrast, in more conventional lock-based
93 schemes, readers must use heavy-weight synchronization in order to
95 This is because lock-based updaters typically update data items in place,
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/Documentation/filesystems/
Dproc.txt1 ------------------------------------------------------------------------------
3 ------------------------------------------------------------------------------
9 ------------------------------------------------------------------------------
11 Kernel version 2.4.0-test11-pre4
12 ------------------------------------------------------------------------------
16 -----------------
23 1.1 Process-Specific Subdirectories
35 3 Per-Process Parameters
36 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
38 3.2 /proc/<pid>/oom_score - Display current oom-killer score
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/Documentation/admin-guide/cgroup-v1/
Dcpusets.rst9 - Portions Copyright (c) 2004-2006 Silicon Graphics, Inc.
10 - Modified by Paul Jackson <pj@sgi.com>
11 - Modified by Christoph Lameter <cl@linux.com>
12 - Modified by Paul Menage <menage@google.com>
13 - Modified by Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
39 ----------------------
43 an on-line node that contains memory.
52 Documentation/admin-guide/cgroup-v1/cgroups.rst.
55 include CPUs in its CPU affinity mask, and using the mbind(2) and
71 ----------------------------
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