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/Documentation/devicetree/bindings/mtd/
Dhisi504-nand.txt5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
[all …]
Dgpmi-nand.txt1 * Freescale General-Purpose Media Interface (GPMI)
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
20 - dma-names: Must be "rx-tx".
21 - clocks : clocks phandle and clock specifier corresponding to each clock
[all …]
Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v4.0
24 brcm,brcmnand-v5.0
25 brcm,brcmnand-v6.0
26 brcm,brcmnand-v6.1
27 brcm,brcmnand-v6.2
[all …]
Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
17 - nxp,rd_low: RD_LOW
18 - nxp,wr_high: WR_HIGH
[all …]
Dnxp-spifi.txt4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
19 - resets : phandle + reset specifier
22 compatible property as specified in bindings/mtd/jedec,spi-nor.txt
25 - spi-cpol : Controller only supports mode 0 and 3 so either
[all …]
Ddenali-nand.txt4 - compatible : should be one of the following:
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
8 - reg : should contain registers location and length for data and reg.
9 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
10 - #address-cells: should be 1. The cell encodes the chip select connection.
11 - #size-cells : should be 0.
12 - interrupts : The interrupt number.
13 - clocks: should contain phandle of the controller core clock, the bus
[all …]
Dnvidia-tegra20-nand.txt4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
14 - reset-names: Must include the following entries:
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Dmarvell-nand.txt4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
15 - #size-cells: shall be set to 0.
[all …]
Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
[all …]
/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt9 io with 3-byte and 4-byte addressing support.
18 - #address-cells:
21 - #size-cells:
24 - compatible:
26 "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
29 "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
30 "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs
32 - reg:
36 - reg-names:
[all …]
Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
19 depends on the interrupt controller.
21 - dmas : Two or more DMA channel specifiers following the convention outlined
[all …]
Dspi-davinci.txt4 Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt4 - name : Should be ifc
5 - compatible : should contain "fsl,ifc". The version of the integrated
9 - #address-cells : Should be either two or three. The first cell is the
12 - #size-cells : Either one or two, depending on how large each chipselect
14 - reg : Offset and length of the register set for the device
15 - interrupts: IFC may have one or two interrupts. If two interrupt
17 interrupt (CM_EVTER_STAT), and the second is the NAND
18 interrupt (NAND_EVTER_STAT). If there is only one,
19 that interrupt reports both types of event.
21 - little-endian : If this property is absent, the big-endian mode will
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-timer.txt4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
10 - fsl,available-ranges: use <start count> style section to define which
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
19 /* Note that this requires #interrupt-cells to be 4 */
21 compatible = "fsl,mpic-global-timer";
24 /* Another AMP partition is using timers 0 and 1 */
25 fsl,available-ranges = <2 2>;
32 compatible = "fsl,mpic-global-timer";
/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.txt8 For SoC, use the compatible string "mediatek,mt7628-wmac" and the following
11 - reg: Address and length of the register set for the device.
12 - interrupts: Main device interrupt
16 - ieee80211-freq-limit: See ieee80211.txt
17 - mediatek,mtd-eeprom: Specify a MTD partition + offset containing EEPROM data
23 - led: Properties for a connected LED
25 - led-sources: See Documentation/devicetree/bindings/leds/common.txt
32 ieee80211-freq-limit = <5000000 6000000>;
33 mediatek,mtd-eeprom = <&factory 0x8000>;
36 led-sources = <2>;
[all …]
/Documentation/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
75 +---+---+---+---------------+
79 +---+---+---+---------------+
81 +---+---+---+---------------+
[all …]
Dhvcs.rst24 3.1 Built-in:
40 ppc64 system. Physical hardware consoles per partition are not practical
55 major and minor numbers are associated with each vty-server. Directions
68 built into the kernel. If not, the default can be over-ridden by inserting
71 3.1 Built-in:
72 -------------
77 Device Drivers --->
78 Character devices --->
84 -----------
89 Device Drivers --->
[all …]
/Documentation/scsi/
Daha152x.txt2 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
4 Copyright 1993-1999 Jürgen Fischer <fischer@norbit.de>
9 bottom-half handler complete()).
20 IRQ interrupt level (9-12; default 11)
21 SCSI_ID scsi id of controller (0-7; default 7)
31 -DAUTOCONF
32 use configuration the controller reports (AHA-152x only)
34 -DSKIP_BIOSTEST
35 Don't test for BIOS signature (AHA-1510 or disabled BIOS)
37 -DSETUP0="{ IOPORT, IRQ, SCSI_ID, RECONNECT, PARITY, SYNCHRONOUS, DELAY, EXT_TRANS }"
[all …]
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
17 For Tegra210 must contain "nvidia,tegra210-pmc"
18 - reg : Offset and length of the register set for the device
[all …]
/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
[all …]
/Documentation/power/
Dswsusp.rst15 ...bye bye root partition.
34 Swap partition:
47 - If you feel ACPI works pretty well on your system, you might try::
51 - If you would like to write hibernation image to swap and then suspend
56 - If you have SATA disks, you'll need recent kernels with SATA suspend
58 are built into kernel -- not modules. [There's way to make
68 - The resume process checks for the presence of the resume device,
72 - The resume process may be triggered in two ways:
81 read-only) otherwise data may be corrupted.
87 Last revised: 2003-10-20 by Pavel Machek
[all …]
/Documentation/admin-guide/
Dinit.rst6 Some high-level reasons for failure (listed roughly in order of execution)
20 (and ``root=`` kernel parameter points to the correct partition),
23 to be pre-loaded by an initrd)
24 C) Possibly a conflict in ``console= setup`` --> initial console unavailable.
26 missing interrupt-based configuration).
29 ``/lib/ld-linux.so.2`` missing or broken. Use
30 ``readelf -d <INIT>|grep NEEDED`` to find out which libraries are required.
33 In case you tried loading a non-binary file here (shell script?),
37 non-script binary such as ``/bin/sh`` and confirm its successful execution.
46 - Implement the various ``run_init_process()`` invocations via a struct array
[all …]
/Documentation/locking/
Dlockdep-design.rst8 Lock-class
9 ----------
19 The validator tracks the 'usage state' of lock-classes, and it tracks
20 the dependencies between different lock-classes. Lock usage indicates
22 dependency can be understood as lock order, where L1 -> L2 suggests that
29 A lock-class's behavior is constructed by its instances collectively:
30 when the first instance of a lock-class is used after bootup the class
33 the class. A lock-class does not go away when a lock instance does, but
39 -----
41 The validator tracks lock-class usage history and divides the usage into
[all …]
/Documentation/ABI/stable/
Dsysfs-driver-ib_srp1 What: /sys/class/infiniband_srp/srp-<hca>-<port_number>/add_target
4 Contact: linux-rdma@vger.kernel.org
7 a comma-separated list of login parameters to this sysfs
9 * id_ext, a 16-digit hexadecimal number specifying the eight
10 byte identifier extension in the 16-byte SRP target port
13 * ioc_guid, a 16-digit hexadecimal number specifying the eight
14 byte I/O controller GUID portion of the 16-byte target port
16 * dgid, a 32-digit hexadecimal number specifying the
18 * pkey, a four-digit hexadecimal number specifying the
19 InfiniBand partition key.
[all …]

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