Searched full:latency (Results 1 – 25 of 169) sorted by relevance
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| /Documentation/devicetree/bindings/opp/ |
| D | qcom-nvmem-cpufreq.txt | 151 clock-latency-ns = <200000>;
157 clock-latency-ns = <200000>;
163 clock-latency-ns = <200000>;
169 clock-latency-ns = <200000>;
175 clock-latency-ns = <200000>;
181 clock-latency-ns = <200000>;
187 clock-latency-ns = <200000>;
193 clock-latency-ns = <200000>;
199 clock-latency-ns = <200000>;
205 clock-latency-ns = <200000>;
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| D | sun50i-nvmem-cpufreq.txt | 47 clock-latency-ns = <244144>; /* 8 32k periods */
58 clock-latency-ns = <244144>; /* 8 32k periods */
69 clock-latency-ns = <244144>; /* 8 32k periods */
80 clock-latency-ns = <244144>; /* 8 32k periods */
92 clock-latency-ns = <244144>; /* 8 32k periods */
101 clock-latency-ns = <244144>; /* 8 32k periods */
110 clock-latency-ns = <244144>; /* 8 32k periods */
119 clock-latency-ns = <244144>; /* 8 32k periods */
128 clock-latency-ns = <244144>; /* 8 32k periods */
137 clock-latency-ns = <244144>; /* 8 32k periods */
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| D | opp.txt | 135 - clock-latency-ns: Specifies the maximum possible transition latency (in
212 clock-latency-ns = <300000>;
219 clock-latency-ns = <310000>;
224 clock-latency-ns = <290000>;
291 clock-latency-ns = <300000>;
298 clock-latency-ns = <310000>;
304 lock-latency-ns = <290000>;
367 clock-latency-ns = <300000>;
374 clock-latency-ns = <310000>;
380 clock-latency-ns = <290000>;
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| /Documentation/devicetree/bindings/arm/ |
| D | idle-states.txt | 31 Idle state parameters (e.g. entry latency) are platform specific and need to be
53 | latency |
55 | latency |
57 |<------- wakeup-latency ------->|
65 event conditions. The abort latency is assumed to be negligible
79 entry-latency: Worst case latency required to enter the idle state. The
80 exit-latency may be guaranteed only after entry-latency has passed.
85 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
87 to be entry-latency + exit-latency.
99 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
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| D | l2c2x0.yaml | 66 arm,data-latency:
67 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
69 without setup latency control should use a value of 0.
78 arm,tag-latency:
79 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
80 read, write and setup latencies. Controllers without setup latency control
81 should use 0. Controllers without separate read and write Tag RAM latency
91 arm,dirty-latency:
92 description: Cycles of latency for Dirty RAMs. This is a single cell.
244 arm,data-latency = <1 1 1>;
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.txt | 13 - entry-latency-us
16 Definition: u32 value representing worst case latency in
18 The exit-latency-us duration may be guaranteed
19 only after entry-latency-us has passed.
21 - exit-latency-us
24 Definition: u32 value representing worst case latency
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| /Documentation/power/ |
| D | pm_qos_interface.rst | 11 2. the per-device PM QoS framework provides the API to manage the per-device latency
16 * latency: usec
95 2. PM QoS per-device latency and flags framework
99 maintained along with the aggregated targets of resume latency and active
100 state latency tolerance (in microseconds) and the third one is for PM QoS flags.
103 The target values of resume latency and active state latency tolerance are
155 Add a request to the device's PM QoS list of resume latency constraints and
161 PM QoS list of resume latency constraints and remove sysfs attribute
189 Active state latency tolerance
198 If there is a latency tolerance control mechanism for a given device available
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| /Documentation/arm/omap/ |
| D | omap_pm.rst | 6 authors use these functions to communicate minimum latency or
17 latency framework or something else;
20 latency and throughput, rather than units which are specific to OMAP
34 1. Set the maximum MPU wakeup latency::
38 2. Set the maximum device wakeup latency::
42 3. Set the maximum system DMA transfer start latency (CORE pwrdm)::
88 latency, and the set_max_dev_wakeup_lat() function to constrain the
89 device wakeup latency (from clk_enable() to accessibility). For
92 /* Limit MPU wakeup latency */
96 /* Limit device powerdomain wakeup latency */
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| /Documentation/networking/ |
| D | tcp-thin.txt | 9 on the data delivery latency, packet loss can be devastating for
21 In order to reduce application-layer latency when packets are lost,
22 a set of mechanisms has been made, which address these latency issues
45 "Improving latency for interactive, thin-stream applications over
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| /Documentation/trace/ |
| D | hwlat_detector.rst | 2 Hardware Latency Detector
14 kernel is highly latency sensitive.
24 The hardware latency detector works by hogging one of the cpus for configurable
40 redefine the threshold in microseconds (us) above which latency spikes will
74 - tracing_threshold - minimum latency value to be considered (usecs)
75 - tracing_max_latency - maximum hardware latency actually observed (usecs)
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| D | ftrace.rst | 28 There's latency tracing to examine what occurs between interrupts
163 Some of the tracers record the max latency.
167 recorded if the latency is greater than the value in this file
170 By echoing in a time into this file, no latency will be recorded
175 Some latency tracers will record a trace whenever the
176 latency is greater than the number in this file.
598 Directory for the Hardware Latency Detector.
599 See "Hardware Latency Detector" section below.
707 The Hardware Latency tracer is used to detect if the hardware
708 produces any latency. See "Hardware Latency Detector" section
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | nvidia,tegra124-cpufreq.txt | 17 - clock-latency: Specify the possible maximum transition latency for clock,
36 clock-latency = <300000>;
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| D | cpufreq-dt.txt | 17 - clock-latency: Specify the possible maximum transition latency for clock,
39 clock-latency = <61036>; /* two CLK32 periods */
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| D | cpufreq-spear.txt | 13 - clock-latency: Specify the possible maximum transition latency for clock, in
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 5 states. Idle states have different enter/exit latency and residency values.
31 state. Retention may have a slightly higher latency than Standby.
52 power modes possible at this state is vast, the exit latency and the residency
78 entry-latency-us = <150>;
79 exit-latency-us = <200>;
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| /Documentation/block/ |
| D | kyber-iosched.rst | 11 Target latency for reads (in nanoseconds).
15 Target latency for synchronous writes (in nanoseconds).
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| D | bfq-iosched.rst | 6 low-latency capabilities. In addition to cgroups support (blkio or io
10 low latency for time-sensitive applications, such as audio or video
16 In its default configuration, BFQ privileges latency over
17 throughput. So, when needed for achieving a lower latency, BFQ builds
20 throughput at all times, then do switch off all low-latency heuristics
23 latency and throughput, or on how to maximize throughput.
81 Low latency for interactive applications
102 Low latency for soft real-time applications
105 players/streamers, enjoy a low latency and a low drop rate, regardless
204 guaranteeing low latency or fairness. In these cases, overall
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| /Documentation/scsi/ |
| D | link_power_management_policy.txt | 8 sacrifice some performance due to increased latency
17 state, thus improving latency over min_power setting.
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 107 next wakeup event, or there are strict latency constraints preventing any of the
135 *exit latency*. The target residency is the minimum time the hardware must
140 latency, in turn, is the maximum time it will take a CPU asking the processor
142 wakeup from that state. Note that in general the exit latency also must cover
310 Then, the governor computes an extra latency limit to help "interactive"
311 workloads. It uses the observation that if the exit latency of the selected
317 of the extra latency limit is the predicted idle duration itself which
320 complete. The result of that division is compared with the latency limit coming
323 exit latency.
327 the predicted idle duration and the exit latency of it with the computed latency
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-power | 209 contains the PM QoS resume latency limit for the given device,
214 the PM QoS resume latency may be arbitrary and the special value
215 "n/a" means that user space cannot accept any resume latency at
229 contains the PM QoS active state latency tolerance limit for the
231 latency the device can suffer without any visible adverse
233 string "any", the latency does not matter to user space at all,
234 but hardware should not be allowed to set the latency tolerance
238 access latency for the device may be determined automatically
241 latency tolerance requirements from the kernel side.
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| /Documentation/networking/device_drivers/intel/ |
| D | e1000e.rst | 53 vector can generate per second. Increasing ITR lowers latency at the cost of
60 but will increase latency as packets are not processed as quickly.
64 all traffic types, but lacking in small packet performance and latency.
77 "Bulk traffic", for large amounts of packets of normal size; "Low latency",
79 packets; and "Lowest latency", for almost completely small packets or
83 Turns off any interrupt moderation and may improve small packet latency.
88 very low latency. This can sometimes cause extra CPU utilization. If
89 planning on deploying e1000e in a latency sensitive environment, this
94 the "Low latency" or "Lowest latency" class, the InterruptThrottleRate is
108 latency as packets are not processed as quickly.
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| D | e1000.rst | 107 but will increase latency as packets are not processed as quickly.
111 all traffic types,but lacking in small packet performance and latency.
124 "Bulk traffic", for large amounts of packets of normal size; "Low latency",
126 packets; and "Lowest latency", for almost completely small packets or
131 latency" or "Lowest latency" class, the InterruptThrottleRate is increased
134 For situations where low latency is vital such as cluster or
135 grid computing, the algorithm can reduce latency even more when
138 70000 for traffic in class "Lowest latency".
147 and may improve small packet latency, but is generally not suitable
215 extra latency to frame reception and can end up decreasing the throughput
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| /Documentation/admin-guide/mm/ |
| D | ksm.rst | 97 latency to access of shared pages. Systems with more nodes, at
99 lower latency of setting 0. Smaller systems, which need to
136 deduplication limit to avoid high latency for virtual memory
144 latency for certain virtual memory operations happening during
147 memory operations. The scheduler latency of other tasks not
156 lower latency, but they will make ksmd use more CPU during the
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| /Documentation/usb/ |
| D | dwc3.rst | 49 Latency:
51 There should be no increase in latency since the interrupt-thread has a
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| /Documentation/networking/device_drivers/chelsio/ |
| D | cxgb.txt | 34 coalescing parameters, allowing the driver to dynamically adapt the latency
50 After disabling adaptive-rx, the timer latency value will be set to 50us.
51 You may set the timer latency after disabling adaptive-rx:
55 An example to set the timer latency value to 100us on eth0:
59 You may also provide a timer latency value while disabling adaptive-rx:
63 If adaptive-rx is disabled and a timer latency value is specified, the timer
67 To view the status of the adaptive-rx and timer latency values:
114 Setting PCI Latency Timer:
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