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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
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| D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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| D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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| D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
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| D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
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| D | img,meta-intc.txt | 8 - compatible: Specifies the compatibility list for the interrupt controller.
9 The type shall be <string> and the value shall include "img,meta-intc".
11 - num-banks: Specifies the number of interrupt banks (each of which can
14 - interrupt-controller: The presence of this property identifies the node
17 - #interrupt-cells: Specifies the number of cells needed to encode an
20 - #address-cells: Specifies the number of cells needed to encode an
22 'interrupt-map' nodes do not have to specify a parent unit address.
26 - no-mask: The controller doesn't have any mask registers.
32 - <1st-cell>: The interrupt-number that identifies the interrupt source.
34 - <2nd-cell>: The Linux interrupt flags containing level-sense information,
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| D | amazon,al-fic.txt | 5 - compatible: should be "amazon,al-fic"
6 - reg: physical base address and size of the registers
7 - interrupt-controller: identifies the node as an interrupt controller
8 - #interrupt-cells : must be 2. Specifies the number of cells needed to encode
9 an interrupt source. Supported trigger types are low-to-high edge
10 triggered and active high level-sensitive.
11 - interrupts: describes which input line in the interrupt parent, this
20 amazon_fic: interrupt-controller@fd8a8500 {
21 compatible = "amazon,al-fic";
22 interrupt-controller;
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| D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
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| D | fsl-imx-gpio.txt | 4 - compatible : Should be "fsl,<soc>-gpio"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should be the port interrupt shared by all 32 pins, if
9 - gpio-controller : Marks the device node as a gpio controller.
10 - #gpio-cells : Should be two. The first cell is the pin number and
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
16 The second cell bits[3:0] is used to specify trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
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| D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
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| D | sodaville.txt | 14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
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| D | gpio-zynq.txt | 2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"
10 - clocks : Clock specifier (see clock bindings for details)
11 - gpio-controller : Marks the device node as a GPIO controller.
12 - interrupts : Interrupt specifier (see interrupt bindings for
14 - interrupt-controller : Marks the device node as an interrupt controller.
15 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
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| D | gpio-omap.txt | 4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
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| D | gpio-xlp.txt | 10 -------------------
12 - compatible: Should be one of the following:
13 - "netlogic,xlp832-gpio": For Netlogic XLP832
14 - "netlogic,xlp316-gpio": For Netlogic XLP316
15 - "netlogic,xlp208-gpio": For Netlogic XLP208
16 - "netlogic,xlp980-gpio": For Netlogic XLP980
17 - "netlogic,xlp532-gpio": For Netlogic XLP532
18 - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
19 - reg: Physical base address and length of the controller's registers.
20 - #gpio-cells: Should be two. The first cell is the pin number and the second
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| D | gpio-vf610.txt | 8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
21 The second cell bits[3:0] is used to specify trigger type and level flags:
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| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
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| D | gpio-mxs.txt | 8 will be represented as sub-nodes of MXS pinctrl node.
11 - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
21 The second cell bits[3:0] is used to specify trigger type and level flags:
22 1 = low-to-high edge triggered.
23 2 = high-to-low edge triggered.
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| D | gpio-uniphier.txt | 4 - compatible: Should be "socionext,uniphier-gpio".
5 - reg: Specifies offset and length of the register set for the device.
6 - gpio-controller: Marks the device node as a GPIO controller.
7 - #gpio-cells: Should be 2. The first cell is the pin number and the second
9 - interrupt-controller: Marks the device node as an interrupt controller.
10 - #interrupt-cells: Should be 2. The first cell defines the interrupt number.
12 1 = low-to-high edge triggered
13 2 = high-to-low edge triggered
14 4 = active high level-sensitive
15 8 = active low level-sensitive
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| D | gpio-mvebu.txt | 5 - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6 "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
8 "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9 Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
12 "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
15 "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
17 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
20 - reg: Address and length of the register set for the device. Only one
21 entry is expected, except for the "marvell,armadaxp-gpio" variant
23 one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
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| /Documentation/virt/kvm/devices/ |
| D | xics.txt | 11 sources, each identified by a 20-bit source number, and a set of
22 least-significant end of the word:
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
43 bitfields, starting from the least-significant end of the word:
54 * Level sensitive flag, 1 bit
55 This bit is 1 for a level-sensitive interrupt source, or 0 for
56 edge-sensitive (or MSI).
60 regardless of its priority), for example by the ibm,int-off RTAS
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom-pm8xxx.txt | 1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
16 - #address-cells:
21 - #size-cells:
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
39 number. The 2nd cell is the trigger type and level flags
42 1 = low-to-high edge triggered
43 2 = high-to-low edge triggered
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| /Documentation/virt/ |
| D | paravirt_ops.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low level critical instructions and high level
17 functionalities in various areas. pv-ops allows for optimizations at run
18 time by enabling binary patching of the low-ops critical operations
23 - simple indirect call
24 These operations correspond to high level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low level critical instructions. They
32 - a set of macros for hand written assembly code
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 - reg: Should contain the physical address of the GPIO module's registers.
13 - gpio-controller: Marks the device node as a GPIO controller.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
17 - interrupts : The interrupt outputs from the controller. One interrupt per
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| /Documentation/ia64/ |
| D | fsys.rst | 2 Light-weight System Calls for IA-64
5 Started: 13-Jan-2003
7 Last update: 27-Sep-2003
9 David Mosberger-Tang
14 "fsys-mode". To recap, the normal states of execution are:
16 - kernel mode:
18 switched over to kernel memory. The user-level state is saved
19 in a pt-regs structure at the top of the kernel memory stack.
21 - user mode:
23 user memory. The user-level state is contained in the
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