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| /Documentation/infiniband/ |
| D | core_locking.rst | 7 both low-level drivers that sit below the midlayer and upper level
13 With the following exceptions, a low-level driver implementation of
29 The corresponding functions exported to upper level protocol
47 used by low-level drivers to dispatch asynchronous events through
53 All of the methods in struct ib_device exported by a low-level
54 driver must be fully reentrant. The low-level driver is required to
61 Because low-level drivers are reentrant, upper level protocol
71 A low-level driver must not perform a callback directly from the
73 allowed for a low-level driver to call a consumer's completion event
74 handler directly from its post_send method. Instead, the low-level
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| /Documentation/devicetree/bindings/power/ |
| D | qcom,rpmpd.txt | 18 Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for
25 opp-level values specified in the OPP tables for RPMh power domains
38 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
42 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
46 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
50 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
54 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
58 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
62 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
66 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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| /Documentation/networking/ |
| D | netif-msg.txt | 3 NETIF Msg Level
5 The design of the network interface message level setting.
15 integer variable that controls the debug message level. The message
16 level ranged from 0 to 7, and monotonically increased in verbosity.
18 The message level was not precisely defined past level 3, but were
19 always implemented within +-1 of the specified level. Drivers tended
20 to shed the more verbose level messages as they matured.
30 Initially this message level variable was uniquely named in each driver
39 Using an ioctl() call to modify the level.
40 Per-interface rather than per-driver message level setting.
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| /Documentation/devicetree/bindings/power/supply/ |
| D | da9150-fg.txt | 7 - dlg,update-interval: Interval time (milliseconds) between battery level checks.
8 - dlg,warn-soc-level: Battery discharge level (%) where warning event raised.
10 - dlg,crit-soc-level: Battery discharge level (%) where critical event raised.
11 This value should be lower than the warning level.
21 dlg,warn-soc-level = /bits/ 8 <15>;
22 dlg,crit-soc-level = /bits/ 8 <5>;
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| /Documentation/devicetree/bindings/arm/socionext/ |
| D | cache-uniphier.txt | 4 All of them have a level 2 cache controller, and some have a level 3 cache
16 - cache-level: specifies the level in the cache hierarchy. The value should
20 - next-level-cache: phandle to the next level cache if present. The next level
24 indicated correctly with "next-level-cache" properties.
35 cache-level = <2>;
47 cache-level = <2>;
48 next-level-cache = <&l3>;
59 cache-level = <3>;
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 58 next-level-cache = <&L2_0>;
62 next-level-cache = <&L3_0>;
74 next-level-cache = <&L2_100>;
78 next-level-cache = <&L3_0>;
87 next-level-cache = <&L2_200>;
91 next-level-cache = <&L3_0>;
100 next-level-cache = <&L2_300>;
104 next-level-cache = <&L3_0>;
113 next-level-cache = <&L2_400>;
117 next-level-cache = <&L3_0>;
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| /Documentation/x86/x86_64/ |
| D | 5level-paging.rst | 4 5-level paging
9 Original x86-64 was limited by 4-level paing to 256 TiB of virtual address
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
31 In this case additional page table level -- p4d -- will be folded at
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
39 information. It collides with valid pointers with 5-level paging and
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| /Documentation/ABI/obsolete/ |
| D | sysfs-bus-usb | 1 What: /sys/bus/usb/devices/.../power/level
7 power/level. This file holds a power-level setting for
17 level. The "on" level is meant for administrative uses.
23 left in the "on" level. Although the USB spec requires
26 initializes all non-hub devices in the "on" level. Some
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| /Documentation/devicetree/bindings/opp/ |
| D | qcom-opp.txt | 11 "operating-points-v2-qcom-level"
16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level
18 a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.txt | 3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
15 - cache-level: Should be set to 2 for a level 2 cache
30 - next-level-cache: phandle to the next level cache if present.
42 cache-level = <2>;
49 next-level-cache = <&L25 &L40 &L36>;
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| /Documentation/scsi/ |
| D | megaraid.txt | 11 interfaces with the applications on one side and all the low level drivers
16 i. Avoid duplicate code from the low level drivers.
17 ii. Unburden the low level drivers from having to export the
21 multiple low level drivers.
24 ioctl commands. But this module is envisioned to handle all user space level
53 module acts as a registry for low level hba drivers. The low level drivers
59 The lower level drivers now understand only a new improved ioctl packet called
68 can easily be more than one. But since megaraid is the only low level driver
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter-104-quad-8 | 5 Active level of index input Signal Y; irrelevant in
26 A logic low level is the active level at this index
28 is performed directly on the active level of the index
33 quadrature clock mode. The active level is configured
36 quadrature clock on the active level of the index input.
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| /Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 3 The level-2 cache controller plays an important role in reducing memory latency
5 Level-2 cache controller in general enhances overall system performance
19 - cache-level : Should be set to 2 for a level 2 cache.
27 cache-level = <2>;
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| /Documentation/core-api/ |
| D | genericirq.rst | 36 - Level type
51 This split implementation of high-level IRQ handlers allows us to
59 and low-level hardware logic, and it also leads to unnecessary code
61 ``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
69 and only need to add the chip-level specific code. The separation is
74 Each interrupt descriptor is assigned its own high-level flow handler,
75 which is normally one of the generic implementations. (This high-level
82 IRQ-flow implementation for 'level type' interrupts and add a
102 1. High-level driver API
104 2. High-level IRQ flow handlers
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| /Documentation/admin-guide/mm/ |
| D | numaperf.rst | 99 by the last memory level in the hierarchy. The system meanwhile uses
103 The term "far memory" is used to denote the last level memory in the
104 hierarchy. Each increasing cache level provides higher performing
108 This numbering is different than CPU caches where the cache level (ex:
109 L1, L2, L3) uses the CPU-side view where each increased level is lower
110 performing. In contrast, the memory cache level is centric to the last
111 level memory, so the higher numbered cache level corresponds to memory
117 accesses the next level of memory until there is either a hit in that
118 cache level, or it reaches far memory.
135 The attributes for each level of cache is provided under its cache
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| /Documentation/media/v4l-drivers/ |
| D | pvrusb2.rst | 29 1. Low level wire-protocol implementation with the device.
34 3. High level hardware driver implementation which coordinates all
38 tear-down, arbitration, and interaction with high level
42 5. High level interfaces which glue the driver to various published
54 right now the V4L high level interface is the most complete, the
55 sysfs high level interface will work equally well for similar
57 possible to produce a DVB high level interface that can sit right
83 here. Hotplugging is ultimately coordinated here. All high level
116 access to the driver should be through one of the high level
118 level interfaces are restricted to the API defined in
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| /Documentation/ia64/ |
| D | fsys.rst | 18 switched over to kernel memory. The user-level state is saved
23 user memory. The user-level state is contained in the
28 interruption-handlers start execution in. The user-level
34 - execution is at privilege level 0 (most-privileged)
36 - CPU registers may contain a mixture of user-level and kernel-level
38 security-sensitive kernel-level state is leaked back to
39 user-level)
46 in fsys-mode (they point to the user-level stacks, which may
51 privilege level is at level 0, this means that fsys-mode requires some
58 Linux operates in fsys-mode when (a) the privilege level is 0 (most
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 38 - <2nd-cell>: The level-sense information, encoded using the Linux interrupt
44 4 = active-high level-sensitive (required for perip irqs)
45 8 = active-low level-sensitive
73 interrupts = <18 4 /* level */>, /* Syswakes */
74 <30 4 /* level */>, /* Peripheral 0 (RTC) */
75 <29 4 /* level */>, /* Peripheral 1 (IR) */
76 <31 4 /* level */>; /* Peripheral 2 (WDT) */
102 // Interrupt source SysWake 0 that is active-low level-sensitive
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| D | snps,archs-idu-intc.txt | 3 This optional 2nd level interrupt controller can be used in SMP configurations
18 - bits[3:0] trigger type and level flags
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
23 When no second cell is specified, the interrupt is assumed to be level
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| /Documentation/scheduler/ |
| D | sched-nice-design.rst | 12 scheduler, (otherwise we'd have done it long ago) because nice level
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
34 -*----------------------------------*-----> [nice level]
59 within the constraints of HZ and jiffies and their nasty design level
63 about Linux's nice level support was its assymetry around the origo
65 accurately: the fact that nice level behavior depended on the _absolute_
66 nice level as well, while the nice API itself is fundamentally
74 Note that the 'inc' is relative to the current nice level. Tools like
79 depend on the nice level of the parent shell - if it was at nice -10 the
82 A third complaint against Linux's nice level support was that negative
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| /Documentation/misc-devices/ |
| D | bh1770glc.txt | 33 interrupts the delayed work is pushed forward. So, when proximity level goes
69 RW - HI level threshold value. All results above the value
74 RW - LO level threshold value. All results below the value
101 RW - Measurement rate (in Hz) when the level is above threshold
105 RW - Measurement rate (in Hz) when the level is below threshold
112 RW - threshold level which trigs proximity events.
116 RW - threshold level which trigs event immediately
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | pwm-backlight.txt | 19 0 will do. The actual brightness level (PWM duty cycle)
23 - default-brightness-level: The default brightness level (index into the
29 brightness-level array.
41 default-brightness-level = <6>;
57 default-brightness-level = <4096>;
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| /Documentation/media/dvb-drivers/ |
| D | ci.rst | 11 This document describes the usage of the high level CI API as
13 existing low level CI API.
79 The High level CI API
85 With the High Level CI approach any new card with almost any random
110 #define CA_CI 1 /* CI high level interface */
111 #define CA_CI_LINK 2 /* CI link layer level interface */
112 #define CA_CI_PHYS 4 /* CI physical layer level interface */
121 This CI interface follows the CI high level interface, which is not
136 With this High Level CI interface, the interface can be defined with the
139 All these ioctls are also valid for the High level CI interface
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| /Documentation/devicetree/bindings/watchdog/ |
| D | gpio-wdt.txt | 11 - level: Low or high level starts counting WDT timeout,
12 the opposite level disables the WDT. Active level is determined
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| /Documentation/firmware-guide/acpi/ |
| D | video_extension.rst | 16 Export a sysfs interface for user space to control backlight level
32 get the brightness level the firmware thinks it is at;
36 on write, control method _BCM will run to set the requested brightness level;
70 as a "brightness level" indicator. Thus from the user space perspective
109 level through the sysfs interface.
111 Change backlight level in the kernel
115 received a notification, it will set the backlight level accordingly. This does
117 space regardless of whether or not the video module controls the backlight level
121 wants to have full control of the backlight level.
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