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/Documentation/devicetree/bindings/net/
Dcavium-pip.txt10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
32 - compatible: "cavium,octeon-3860-pip-port"
36 - reg: The port number within the interface group.
[all …]
Dbrcm,systemport.txt4 - compatible: should be one of:
5 "brcm,systemport-v1.00"
6 "brcm,systemportlite-v1.00" or
8 - reg: address and length of the register set for the device.
9 - interrupts: interrupts for the device, first cell must be for the rx
11 optional third interrupt cell for Wake-on-LAN can be specified
12 - local-mac-address: Ethernet MAC address (48 bits) of this adapter
13 - phy-mode: Should be a string describing the PHY interface to the
15 - fixed-link: see Documentation/devicetree/bindings/net/fixed-link.txt for
19 - systemport,num-tier2-arb: number of tier 2 arbiters, an integer
[all …]
Dqca,qca7000.txt3 The QCA7000 is a serial-to-powerline bridge with a host interface which could
13 - compatible : Should be "qca,qca7000"
14 - reg : Should specify the SPI chip select
15 - interrupts : The first cell should specify the index of the source
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
22 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
26 - qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
33 The MAC address will be determined using the optional properties
40 #address-cells = <1>;
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Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
11 "control_port": MAC configuration space region
18 - interrupts: Should contain the TSE interrupts and it's mode.
19 - interrupt-names: Should contain the interrupt names
22 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
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Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
16 local-mac-address:
18 - $ref: /schemas/types.yaml#definitions/uint8-array
19 - items:
20 - minItems: 6
23 Specifies the MAC address that was assigned to the network device.
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Dopencores-ethoc.txt1 * OpenCores MAC 10/100 Mbps
4 - compatible: Should be "opencores,ethoc".
5 - reg: two memory regions (address and length),
8 - interrupts: interrupt for the device.
11 - clocks: phandle to refer to the clk used as per
12 Documentation/devicetree/bindings/clock/clock-bindings.txt
20 local-mac-address = [00 50 c2 13 6f 00];
Dsocionext,uniphier-ave4.txt7 - compatible: Should be
8 - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
9 - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
10 - "socionext,uniphier-ld11-ave4" : for LD11 SoC
11 - "socionext,uniphier-ld20-ave4" : for LD20 SoC
12 - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC
13 - reg: Address where registers are mapped and size of region.
14 - interrupts: Should contain the MAC interrupt.
15 - phy-mode: See ethernet.txt in the same directory. Allow to choose
17 The acceptable mode is SoC-dependent.
[all …]
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Dmicrochip,lan78xx.txt8 - compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850".
10 The MAC address will be determined using the optional properties
14 - microchip,led-modes: a 0..4 element vector, with each element configuring
16 are defined in "include/dt-bindings/net/microchip-lan78xx.h".
22 usb-port@1 {
25 #address-cells = <1>;
26 #size-cells = <0>;
28 usb-port@1 {
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
Dhisilicon-hns-nic.txt4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
20 +-+-+-+---+-+-+-+-+-+-+
24 (0,1) (2-7)
[all …]
Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
Ddavinci_emac.txt7 - compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
8 "ti,dm816-emac"
9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
14 - interrupts: interrupt mapping for the davinci emac interrupts sources:
21 - phy-handle: See ethernet.txt file in the same directory.
23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
[all …]
Dsocionext-netsec.txt4 - compatible: Should be "socionext,synquacer-netsec"
5 - reg: Address and length of the control register area, followed by the
6 address and length of the EEPROM holding the MAC address and
8 - interrupts: Should contain ethernet controller interrupt
9 - clocks: phandle to the PHY reference clock
10 - clock-names: Should be "phy_ref_clk"
11 - phy-mode: See ethernet.txt file in the same directory
12 - phy-handle: See ethernet.txt in the same directory.
14 - mdio device tree subnode: When the Netsec has a phy connected to its local
18 - #address-cells: Must be <1>.
[all …]
Ddavicom-dm9000.txt4 - compatible = "davicom,dm9000";
5 - reg : physical addresses and sizes of registers, must contain 2 entries:
6 first entry : address register,
8 - interrupts : interrupt specifier specific to interrupt controller
11 - davicom,no-eeprom : Configuration EEPROM is not available
12 - davicom,ext-phy : Use external PHY
13 - reset-gpios : phandle of gpio that will be used to reset chip during probe
14 - vcc-supply : phandle of regulator that will be used to enable power to chip
21 interrupt-parent = <&gpn>;
23 local-mac-address = [00 00 de ad be ef];
[all …]
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
Dmacb.txt4 - compatible: Should be "cdns,[<chip>-]{macb|gem}"
5 Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
6 Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
7 Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
8 Use "cdns,np4-macb" for NP4 SoC devices.
9 Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
10 Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
12 Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
13 Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
14 Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
[all …]
Dfsl-fec.txt4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
[all …]
Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
Dwiznet,w5x00.txt9 - compatible: Should be one of the following strings:
13 - reg: Specify the SPI chip select the chip is wired to.
14 - interrupts: Specify the interrupt index within the interrupt controller (referred
15 to above in interrupt-parent) and interrupt type. w5x00 natively
18 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
19 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
24 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
27 - local-mac-address: See ethernet.txt in the same directory.
36 pinctrl-names = "default";
37 pinctrl-0 = <&eth1_pins>;
[all …]
/Documentation/networking/
Ddecnet.txt7 http://www.chygwyn.com/ - Kernel info
8 http://linux-decnet.sourceforge.net/ - Userland tools
9 http://www.sourceforge.net/projects/linux-decnet/ - Status page
32 o Set the MAC address on your ethernet card before starting _any_ other
37 to set the MAC address, see the next section. Also all configurations which
42 You can set a DECnet address on the kernel command line for compatibility
44 If you do st a DECnet address on the command line, it has only one purpose
47 With 2.4 kernels, DECnet would only recognise addresses as local if they
48 were added to the loopback device. In 2.5, any local interface address
49 can be used to loop back to the local machine. Of course this does not
[all …]
Dnetconsole.txt16 It can be used either built-in or as a module. As a built-in,
28 netconsole=[+][src-port]@[src-ip]/[<dev>],[tgt-port]@<tgt-ip>/[tgt-macaddr]
32 src-port source for UDP packets (defaults to 6665)
33 src-ip source IP to use (interface address)
35 tgt-port port for logging agent (6666)
36 tgt-ip IP address for logging agent
37 tgt-macaddr ethernet MAC address for logging agent (broadcast)
57 Built-in netconsole starts immediately after the TCP stack is
59 address.
68 On distributions using a BSD-based netcat version (e.g. Fedora,
[all …]
Dbonding.txt7 Corrections, HA extensions : 2000/10/03-15 :
8 - Willy Tarreau <willy at meta-x.org>
9 - Constantine Gavrilov <const-g at xpert.com>
10 - Chad N. Tindel <ctindel at ieee dot org>
11 - Janice Girouard <girouard at us dot ibm dot com>
12 - Jay Vosburgh <fubar at us dot ibm dot com>
16 - Mitch Williams <mitch.a.williams at intel.com>
29 the original tools from extreme-linux and beowulf sites will not work
114 -----------------------------------------------
130 -------------------------------------
[all …]
/Documentation/devicetree/bindings/edac/
Dsocfpga-eccmgr.txt8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
26 - iram : phandle to On-Chip RAM definition.
[all …]
/Documentation/ABI/testing/
Dsysfs-class-net17 Indicates the address assignment type. Possible values are:
18 0: permanent address
28 Indicates the hardware address size in bytes.
29 Values vary based on the lower-level protocol used by the
33 What: /sys/class/net/<iface>/address
38 Hardware address currently assigned to this interface.
39 Format is a string, e.g: 00:11:22:33:44:55 for an Ethernet MAC
40 address.
47 Bitmask to allow forwarding of link local frames with address
48 01-80-C2-00-00-0X on a bridge device. Only values that set bits
[all …]

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