Searched +full:low +full:- +full:power (Results 1 – 25 of 322) sorted by relevance
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| /Documentation/firmware-guide/acpi/ |
| D | lpit.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Low Power Idle Table (LPIT)
7 To enumerate platform Low Power Idle states, Intel platforms are using
8 “Low Power Idle Table” (LPIT). More details about this table can be
12 Residencies for each low power state can be read via FFH
18 - CPU PKG C10 (Read via FFH interface)
19 - Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
32 This is the lowest possible system power state, achieved only when CPU is in
33 PKG C10 and all functional blocks in PCH are in a low power state.
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-vf610 | 3 Contact: linux-iio@vger.kernel.org
6 available modes are "normal", "high-speed" and "low-power",
12 Contact: linux-iio@vger.kernel.org
15 The two available modes are "high-power" and "low-power",
16 where "low-power" mode is the default mode.
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-stm32-lp.txt | 1 STMicroelectronics STM32 Low-Power Timer PWM
3 STM32 Low-Power Timer provides single channel PWM.
5 Must be a sub-node of an STM32 Low-Power Timer device tree node.
6 See ../mfd/stm32-lptimer.txt for details about the parent node.
9 - compatible: Must be "st,stm32-pwm-lp".
10 - #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
14 - pinctrl-names: Set to "default". An additional "sleep" state can be
15 defined to set pins in sleep state when in low power.
16 - pinctrl-n: Phandle(s) pointing to pin configuration node for PWM,
21 compatible = "st,stm32-lptimer";
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| /Documentation/devicetree/bindings/counter/ |
| D | stm32-lptimer-cnt.txt | 1 STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
3 STM32 Low-Power Timer provides several counter modes. It can be used as:
4 - quadrature encoder to detect angular position and direction of rotary
6 - simple counter from IN1 input signal.
8 Must be a sub-node of an STM32 Low-Power Timer device tree node.
9 See ../mfd/stm32-lptimer.txt for details about the parent node.
12 - compatible: Must be "st,stm32-lptimer-counter".
13 - pinctrl-names: Set to "default". An additional "sleep" state can be
15 - pinctrl-n: List of phandles pointing to pin configuration nodes,
16 to set IN1/IN2 pins in mode of operation for Low-Power
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| /Documentation/devicetree/bindings/usb/ |
| D | pxa-usb.txt | 6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci", "usb-ohci";
28 marvell,enable-port1;
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| /Documentation/admin-guide/pm/ |
| D | sleep-states.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 Sleep states are global low-power states of the entire system in which user
28 Suspend-to-Idle
29 ---------------
31 This is a generic, pure software, light-weight variant of system suspend (also
34 I/O devices into low-power states (possibly lower-power than available in the
38 The system is woken up from this state by in-band interrupts, so theoretically
43 or :ref:`suspend-to-RAM <s2ram>`, or it can be used in addition to any of the
50 -------
54 operating state is lost (the system core logic retains power), so the system can
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77620.txt | 1 MAX77620 Power management IC from Maxim Semiconductor.
4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
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| /Documentation/devicetree/bindings/power/reset/ |
| D | gpio-poweroff.txt | 1 Driver a GPIO line that can be used to turn the power off.
3 The driver supports both level triggered and edge triggered power off.
5 install a handler to power off the system. If the optional properties
9 When the power-off handler is called, the gpio is configured as an
10 output, and drive active, so triggering a level triggered power off
11 condition. This will also cause an inactive->active edge condition, so
12 triggering positive edge triggered power off. After a delay of 100ms,
13 the GPIO is set to inactive, thus causing an active->inactive edge,
14 triggering negative edge triggered power off. After another 100ms
15 delay the GPIO is driver active again. If the power is still on and
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| /Documentation/devicetree/bindings/iio/timer/ |
| D | stm32-lptimer-trigger.txt | 1 STMicroelectronics STM32 Low-Power Timer Trigger
3 STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
6 Must be a sub-node of an STM32 Low-Power Timer device tree node.
7 See ../mfd/stm32-lptimer.txt for details about the parent node.
10 - compatible: Must be "st,stm32-lptimer-trigger".
11 - reg: Identify trigger hardware block. Must be 0, 1 or 2
17 compatible = "st,stm32-lptimer";
20 compatible = "st,stm32-lptimer-trigger";
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6358.txt | 5 which can either be controlled by software (exporting the 74x164 as spi-gpio.
6 See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
10 - compatible : should be "brcm,bcm6358-leds".
11 - #address-cells : must be 1.
12 - #size-cells : must be 0.
13 - reg : BCM6358 LED controller address and size.
16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
18 - brcm,clk-dat-low : Boolean, makes clock and data signals active low.
21 Each LED is represented as a sub-node of the brcm,bcm6358-leds device.
23 LED sub-node required properties:
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| /Documentation/devicetree/bindings/power/supply/ |
| D | max8903-charger.txt | 4 - compatible: "maxim,max8903" for MAX8903 Battery Charger
5 - dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided
6 - uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provid…
9 - cen-gpios: Charge enable pin (active low, output)
10 - chg-gpios: Charger status pin (active low, input)
11 - flt-gpios: Fault pin (active low, output)
12 - dcm-gpios: Current limit mode setting (DC=1 or USB=0, output)
13 - usus-gpios: USB suspend pin (active high, output)
18 max8903-charger {
20 dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.txt | 1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - reg: Must contain an (offset, length) pair of the register set for each
8 entry in reg-names.
9 - reg-names: Must include the following entries:
10 - "pmc"
11 - "wake"
12 - "aotag"
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| /Documentation/driver-api/pm/ |
| D | devices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 Device Power Management Basics
18 :Copyright: |copy| 2010-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
25 Most of the code in Linux is device drivers, so most of the Linux power
26 management (PM) code is also driver-specific. Most drivers will do very
30 This writeup gives an overview of how drivers interact with system-wide
31 power management goals, emphasizing the models and interfaces that are
33 background for the domain-specific work you'd do with any specific driver.
36 Two Models for Device Power Management
39 Drivers will use one or both of these models to put devices into low-power
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| /Documentation/hwmon/ |
| D | ir35221.rst | 9 Addresses scanned: -
13 Author: Samuel Mendoza-Jonas <sam@mendozajonas.com>
17 -----------
19 IR35221 is a Digital DC-DC Multiphase Converter
23 -----------
32 # echo ir35221 0x70 > /sys/bus/i2c/devices/i2c-4/new_device
36 ----------------
44 curr[2-3]_label "iout[1-2]"
45 curr[2-3]_input Measured output current
46 curr[2-3]_crit Critical maximum current
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| D | pmbus.rst | 10 Addresses scanned: -
14 http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146395
20 Addresses scanned: -
24 http://www.onsemi.com/pub_link/Collateral/ADP4000-D.PDF
26 http://www.onsemi.com/pub_link/Collateral/NCP4200-D.PDF
28 http://www.onsemi.com/pub_link/Collateral/JUNE%202009-%20REV.%200.PDF
30 * Lineage Power
34 Addresses scanned: -
52 Addresses scanned: -
70 Addresses scanned: -
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| D | ltc2978.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
44 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
10 * Standalone Power Collapse (Standalone PC or SPC)
11 * Power Collapse (PC)
26 Retention: Retention is a low power state where the core is clock gated and
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
35 to indicate a core entering a power down state without consulting any other
36 cpu or the system resources. This helps save power only on that core. The SPM
37 sequence for this idle state is programmed to power down the supply to the
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| D | qcom,saw2.txt | 3 The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
5 power-controller that transitions a piece of hardware (like a processor or
6 subsystem) into and out of low power modes via a direct connection to
8 system, notifying them when a low power state is entered or exited.
21 - compatible:
27 "qcom,apq8064-saw2-v1.1-cpu"
28 "qcom,msm8974-saw2-v2.1-cpu"
29 "qcom,apq8084-saw2-v2.1-cpu"
31 - reg:
33 Value type: <prop-encoded-array>
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| /Documentation/arm/pxa/ |
| D | mfp.rst | 7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
27 +--------+ +------>| |
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| /Documentation/power/ |
| D | pci.rst | 2 PCI Power Management
7 An overview of concepts and the Linux kernel's interfaces related to PCI power
11 This document only covers the aspects of power management specific to PCI
13 power management refer to Documentation/driver-api/pm/devices.rst and
14 Documentation/power/runtime_pm.rst.
18 1. Hardware and Platform Support for PCI Power Management
19 2. PCI Subsystem and Device Power Management
20 3. PCI Device Drivers and Power Management
24 1. Hardware and Platform Support for PCI Power Management
27 1.1. Native and Platform-Based Power Management
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| /Documentation/devicetree/bindings/leds/irled/ |
| D | spi-ir-led.txt | 8 - compatible: should be "ir-spi-led".
11 - duty-cycle: 8 bit balue that represents the percentage of one period
13 - led-active-low: boolean value that specifies whether the output is
15 - power-supply: specifies the power source. It can either be a regulator
16 or a gpio which enables a regulator, i.e. a regulator-fixed as
18 Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
23 compatible = "ir-spi-led";
25 spi-max-frequency = <5000000>;
26 power-supply = <&vdd_led>;
27 led-active-low;
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| /Documentation/devicetree/bindings/net/ |
| D | sff,sfp.txt | 1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
32 - rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
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| /Documentation/devicetree/bindings/timer/ |
| D | nxp,tpm-timer.txt | 1 NXP Low Power Timer/Pulse Width Modulation Module (TPM)
4 and the generation of PWM signals to control electric motor and power
6 are clocked by an asynchronous clock that can remain enabled in low
7 power modes. TPM can support global counter bus where one TPM drives
12 - compatible : should be "fsl,imx7ulp-tpm"
13 - reg : Specifies base physical address and size of the register sets
15 - interrupts : Should be the clock event device interrupt.
16 - clocks : The clocks provided by the SoC to drive the timer, must contain
17 an entry for each entry in clock-names.
18 - clock-names : Must include the following entries: "ipg" and "per".
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