| /Documentation/devicetree/bindings/mailbox/ |
| D | altera-mailbox.txt | 5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
12 - interrupts : interrupt number. The interrupt specifier format
17 compatible = "altr,mailbox-1.0";
19 interrupt-parent = < &gic_0 >;
21 #mbox-cells = <1>;
25 compatible = "altr,mailbox-1.0";
27 interrupt-parent = < &gic_0 >;
29 #mbox-cells = <1>;
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| D | sti-mailbox.txt | 7 ----------
10 - compatible : Should be "st,stih407-mailbox"
11 - reg : Offset and length of the device's register set
12 - mbox-name : Name of the mailbox
13 - #mbox-cells: : Must be 2
20 - interrupts : Contains the IRQ line for a Rx mailbox
25 compatible = "st,stih407-mailbox";
28 #mbox-cells = <2>;
29 mbox-name = "a9";
33 ------
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| D | hisilicon,hi6220-mailbox.txt | 13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
40 --------
43 compatible = "hisilicon,hi6220-mbox";
46 interrupt-parent = <&gic>;
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| D | mailbox.txt | 9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
35 mbox-names = "pwr-ctrl", "rpc";
42 compatible = "mmio-sram";
45 #address-cells = <1>;
46 #size-cells = <1>;
50 compatible = "client-shmem";
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| D | omap-mailbox.txt | 25 routed to different processor sub-systems on DRA7xx as they are routed through
35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
38 --------------------
39 - compatible: Should be one of the following,
40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
45 - reg: Contains the mailbox register address range (base
47 - interrupts: Contains the interrupt information for the mailbox
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| D | hisilicon,hi3660-mailbox.txt | 9 ----------
12 - compatible: : Shall be "hisilicon,hi3660-mbox"
13 - reg: : Offset and length of the device's register set
14 - #mbox-cells: : Must be 3
21 - interrupts: : Contains the two IRQ lines for mailbox.
26 compatible = "hisilicon,hi3660-mbox";
30 #mbox-cells = <3>;
34 ------
37 - compatible : See the client docs
38 - mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
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| D | ti,secure-proxy.txt | 7 called "threads" or "proxies" - each instance is unidirectional and is
14 --------------------
15 - compatible: Shall be "ti,am654-secure-proxy"
16 - reg-names target_data - Map the proxy data region
17 rt - Map the realtime status region
18 scfg - Map the configuration region
19 - reg: Contains the register map per reg-names.
20 - #mbox-cells Shall be 1 and shall refer to the transfer path
22 - interrupt-names: Contains interrupt names matching the rx transfer path
25 - interrupts: Contains the interrupt information corresponding to
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| D | stm32-ipcc.txt | 1 * STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
9 - compatible: Must be "st,stm32mp1-ipcc"
10 - reg: Register address range (base address and length)
11 - st,proc-id: Processor id using the mailbox (0 or 1)
12 - clocks: Input clock
13 - interrupt-names: List of names for the interrupts described by the interrupt
15 - "rx"
16 - "tx"
17 - "wakeup"
18 - interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
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| D | ti,message-manager.txt | 7 "proxies" - each instance is unidirectional and is instantiated at SoC
13 --------------------
14 - compatible: Shall be: "ti,k2g-message-manager"
15 - reg-names queue_proxy_region - Map the queue proxy region.
16 queue_state_debug_region - Map the queue state debug
18 - reg: Contains the register map per reg-names.
19 - #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that
21 - interrupt-names: Contains interrupt names matching the rx transfer path
24 For ti,k2g-message-manager, this shall contain:
26 - interrupts: Contains the interrupt information corresponding to
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| D | xlnx,zynqmp-ipi-mailbox.txt | 8 +-------------------------------------+
10 +-------------------------------------+
11 +--------------------------------------------------+
15 +--------------------------+ |
18 +--------------------------------------------------+
19 +------------------------------------------+
20 | +----------------+ +----------------+ |
24 | +----------------+ +----------------+ |
27 +------------------------------------------+
33 --------------------
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| D | nvidia,tegra186-hsp.txt | 13 - name : Should be hsp
14 - compatible
17 - "nvidia,tegra186-hsp"
18 - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
19 - reg : Offset and length of the register set for the device.
20 - interrupt-names
22 Contains a list of names for the interrupts described by the interrupt
24 - "doorbell"
25 - "sharedN", where 'N' is a number from zero up to the number of
28 by name, using this interrupt-names property to do so.
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| D | qcom,apcs-kpss-global.txt | 7 - compatible:
11 "qcom,msm8916-apcs-kpss-global",
12 "qcom,msm8996-apcs-hmss-global"
13 "qcom,msm8998-apcs-hmss-global"
14 "qcom,qcs404-apcs-apps-global"
15 "qcom,sc7180-apss-shared"
16 "qcom,sdm845-apss-shared"
17 "qcom,sm8150-apss-shared"
18 "qcom,ipq8074-apcs-apps-global"
20 - reg:
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| D | mtk-gce.txt | 9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
13 - reg: Address range of the GCE unit
14 - interrupts: The interrupt signal from the GCE block
15 - clock: Clocks according to the common clock binding
16 - clock-names: Must be "gce" to stand for GCE clock
17 - #mbox-cells: Should be 3.
26 - mboxes: Client use mailbox to communicate with GCE, it should have this
29 - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
31 sub-system specifiers.
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| D | arm-mhu.txt | 4 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
17 --------------------
18 - compatible: Shall be "arm,mhu" & "arm,primecell"
19 - reg: Contains the mailbox register address range (base
21 - #mbox-cells Shall be 1 - the index of the channel needed.
22 - interrupts: Contains the interrupt information corresponding to
26 --------
29 #mbox-cells = <1>;
32 interrupts = <0 36 4>, /* LP-NonSecure */
33 <0 35 4>, /* HP-NonSecure */
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| /Documentation/devicetree/bindings/serial/ |
| D | nvidia,tegra194-tcu.txt | 4 systems within the Tegra SoC. It is implemented through a mailbox-
10 - name : Should be tcu
11 - compatible
14 - "nvidia,tegra194-tcu"
15 - mbox-names:
16 "rx" - Mailbox for receiving data from hardware UART
17 "tx" - Mailbox for transmitting data to hardware UART
18 - mboxes: Mailboxes corresponding to the mbox-names.
24 - .../mailbox/mailbox.txt
25 - .../mailbox/nvidia,tegra186-hsp.txt
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| /Documentation/devicetree/bindings/dsp/ |
| D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
26 - description: ipg clock
27 - description: ocram clock
28 - description: core clock
30 clock-names:
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.txt | 1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
27 - compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
28 should be "ti,am654-sci" for for TI AM654 SoC
29 - mbox-names:
30 "rx" - Mailbox corresponding to receive path
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,scmi.txt | 2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi"
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
31 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
40 Each protocol supported shall have a sub-node with corresponding compatible
43 mboxes, mbox-names and shmem shall be present in the sub-node corresponding
[all …]
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| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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| /Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
25 clock-names = "clk";
|
| /Documentation/ |
| D | bus-virt-phys-mapping.txt | 11 (see Documentation/DMA-API-HOWTO.txt). They continue
13 must not use them. --davidm 00/12/12
20 The AHA-1542 is a bus-master device, and your patch makes the driver give the
26 so-called "bus address".
29 that is, normal RAM--see later about other details):
31 - CPU untranslated. This is the "physical" address. Physical address
34 - CPU translated address. This is the "virtual" address, and is
38 - bus address. This is the address of memory as seen by OTHER devices,
40 addresses, with each device seeing memory in some device-specific way, but
53 0-2 GB "real memory"
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
66 ------------------------------------------------------------
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | stm32-rproc.txt | 2 -----------------------------------
7 - compatible: Must be "st,stm32mp1-m4"
8 - reg: Address ranges of the RETRAM and MCU SRAM memories used by the
10 - resets: Reference to a reset controller asserting the remote processor.
11 - st,syscfg-holdboot: Reference to the system configuration which holds the
16 - st,syscfg-tz: Reference to the system configuration which holds the RCC trust
23 - interrupts: Should contain the watchdog interrupt
24 - mboxes: This property is required only if the rpmsg/virtio functionality
26 - a channel (a) used to communicate through virtqueues with the
28 Bi-directional channel:
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| /Documentation/scsi/ |
| D | ChangeLog.lpfc | 2 * Please read the associated RELEASE-NOTES file !!!
8 * Fixed build warning for 2.6.12-rc2 kernels: mempool_alloc now
19 * Removed FC_TRANSPORT_PATCHESxxx defines. They're in 2.6.12-rc1.
26 * Added PCI ID for LP10000-S.
31 * Zero-out response sense length in lpfc_scsi_prep_cmnd to prevent
33 - was causing spurious 0710 messages.
55 - stop using volatile. if you need special ordering use memory
57 - switch lpfc_sli_pcimem_bcopy to take void * arguments.
58 - remove typecast for constants - a U postfix marks them
60 - add a MAILBOX_CMD_SIZE macro, as most users of
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| /Documentation/process/ |
| D | email-clients.rst | 7 ---
9 These days most developers use ``git send-email`` instead of regular
19 -------------------
23 attachments, but then the attachments should have content-type
39 Emailed patches should be in ASCII or UTF-8 encoding only.
40 If you configure your email client to send emails with UTF-8 encoding,
43 Email clients should generate and maintain "References:" or "In-Reply-To:"
46 Copy-and-paste (or cut-and-paste) usually does not work for patches
49 copy-and-paste.
61 -----------------------------
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