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/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
Dhisilicon-hns-dsaf.txt30 - reset-field-offset: is offset of reset field. Its value depends on the hardware
41 - cpld-syscon: is syscon handle + register offset pair for cpld register. It is
43 - port-rst-offset: is offset of reset field for each port in dsaf. Its value
45 - port-mode-offset: is offset of port mode field for each port in dsaf. Its
66 reset-field-offset = 0;
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt55 - nvidia,pad-autocal-pull-up-offset-3v3,
56 nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
58 - nvidia,pad-autocal-pull-up-offset-1v8,
59 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
61 - nvidia,pad-autocal-pull-up-offset-3v3-timeout,
62 nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
65 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
66 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
69 - nvidia,pad-autocal-pull-up-offset-sdr104,
70 nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
[all …]
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.txt17 - offset : register offset to the register controlling this LED
37 offset = <0x08>;
45 offset = <0x08>;
53 offset = <0x08>;
61 offset = <0x08>;
68 offset = <0x08>;
75 offset = <0x08>;
82 offset = <0x08>;
89 offset = <0x08>;
/Documentation/trace/
Duprobetracer.rst19 user to calculate the offset of the probepoint in the object.
29 p[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a uprobe
30 r[:[GRP/]EVENT] PATH:OFFSET [FETCHARGS] : Set a return uprobe (uretprobe)
35 on PATH+OFFSET.
37 OFFSET : Offset where the probe is inserted.
42 @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
70 offset, and container-size (usually 32). The syntax is::
72 b<bit-width>@<bit-offset>/<container-size>
86 as below (sets a uprobe at an offset of 0x4245c0 in the executable /bin/bash)::
115 0x46420 is the offset of zfree in object /bin/zsh that is loaded at
[all …]
/Documentation/devicetree/bindings/regulator/
Danatop-regulator.txt6 - anatop-reg-offset: Anatop MFD register offset
14 - anatop-delay-reg-offset: Anatop MFD step time register offset
18 - anatop-enable-bit: Regulator enable bit offset
31 anatop-reg-offset = <0x140>;
34 anatop-delay-reg-offset = <0x170>;
/Documentation/devicetree/bindings/clock/
Darm-syscon-icst.txt9 an ICST clock request after a write to the 32 bit register at an offset
12 writing a special token to another offset in the system controller.
48 - lock-offset: the offset address into the system controller where the
50 - vco-offset: the offset address into the system controller where the
65 lock-offset = <0x20>;
66 vco-offset = <0x0c>;
Dti-clkctrl.txt11 the hardware offset from the clkctrl instance register space. The optional
12 clocks can be specified by clkctrl hardware offset and the index of the
21 offset from the clock domain base and the second being the
41 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
Dxgene.txt49 - csr-offset : Offset to the CSR reset register from the reset address base.
52 - enable-offset : Offset to the enable register from the reset address base.
55 - divider-offset : Offset to the divider CSR register from the divider base.
107 divider-offset = <0x238>;
121 csr-offset = <0x0>;
123 enable-offset = <0x8>;
125 divider-offset = <0x10>;
/Documentation/leds/
Dleds-mlxcpld.rst28 - CPLD reg offset: 0x20
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
48 - CPLD reg offset: 0x22
77 - CPLD reg offset: 0x20
81 - CPLD reg offset: 0x21
85 - CPLD reg offset: 0x23
89 - CPLD reg offset: 0x23
[all …]
/Documentation/devicetree/bindings/mtd/
Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
31 fsl,upm-addr-offset = <16>;
32 fsl,upm-cmd-offset = <8>;
51 fsl,upm-addr-offset = <0x10>;
52 fsl,upm-cmd-offset = <0x08>;
/Documentation/devicetree/bindings/timer/
Dqcom,msm-timer.txt28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
30 cpu-offset + (0x10000 * cpu-nr).
46 cpu-offset = <0x40000>;
/Documentation/devicetree/bindings/power/reset/
Dsyscon-poweroff.txt5 defined by the register map pointed by syscon reference plus the offset
11 - offset: offset in the register map for the poweroff register (in bytes)
28 offset = <0x0>;
Dsyscon-reboot.txt5 defined by the register map pointed by syscon reference plus the offset
11 - offset: offset in the register map for the reboot register (in bytes)
28 offset = <0x0>;
/Documentation/devicetree/bindings/net/can/
Dfsl-flexcan.txt12 - reg : Offset and length of the register set for this device
30 req_gpr is the gpr register offset of CAN stop request.
31 req_bit is the bit offset of CAN stop request.
32 ack_gpr is the gpr register offset of CAN stop acknowledge.
33 ack_bit is the bit offset of CAN stop acknowledge.
/Documentation/devicetree/bindings/reset/
Dsocfpga-reset.txt7 - altr,modrst-offset : Should contain the offset of the first modrst register.
15 altr,modrst-offset = <0x10>;
Dhisilicon,hi3660-reset.txt18 Cell #1 : offset of the reset assert control
20 offset + 4: deassert control register
21 offset + 8: status control register
42 resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
/Documentation/devicetree/bindings/c6x/
Ddscr.txt35 offset of the devstat register
38 offset, start bit, and bitsize of silicon revision field
41 offset and bitmask of RMII reset field. May have multiple tuples if more
46 a lock register. Each tuple consists of the register offset, lock register
50 offset and key values of two "kick" registers used to write protect other
58 a register offset and four cells representing bytes in the register from
73 reg is the offset of the register holding the control bits
90 reg is the offset of the register holding the status bits
97 Offset and default value for register used to set access privilege for
/Documentation/
Dio-mapping.txt31 unsigned long offset)
33 'offset' is the offset within the defined mapping region.
35 creation function yields undefined results. Using an offset
60 unsigned long offset)
86 map_atomic and map functions add the requested offset to the base of the
/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt8 - mediatek,offset: Array contains of register offset and mask
23 mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
/Documentation/bpf/
Dbtf.rst47 __u32 type_off; /* offset of type section */
49 __u32 str_off; /* offset of string section */
118 ``name_off`` in ``struct btf_type`` specifies the offset in the string table.
125 * ``name_off``: any valid offset
152 The ``BTF_INT_OFFSET()`` specifies the starting bit offset to calculate values
155 * btf member bit offset 100 from the start of the structure,
165 * btf member bit offset 102,
234 * ``name_off``: 0 or offset to a valid C identifier
245 __u32 offset;
249 * ``name_off``: offset to a valid C identifier
[all …]
/Documentation/scsi/
Dhptiop.txt8 BAR0 offset Register
12 BAR2 offset Register
27 BAR0 offset Register
42 BAR0 offset Register
48 BAR1 offset Register
60 BAR0 offset Register
63 BAR1 offset Register
92 The value returned from the inbound queue port is an offset
100 allocated in IOP memory, write the offset to inbound queue port. For
108 For requests allocated in IOP memory, the request offset is posted to
/Documentation/power/
Dswsusp-and-swap-files.rst21 and the offset from the beginning of the partition at which the swap file's
22 header is located. For convenience, this offset is expressed in <PAGE_SIZE>
35 offset, in <PAGE_SIZE> units, from the beginning of the partition which
43 and <swap_file_offset> is the offset of the swap header determined by the
45 by the same application that determines the swap file's header offset using the
50 Use a userland suspend application that will set the partition and offset
/Documentation/devicetree/bindings/input/touchscreen/
Dedt-ft5x06.txt45 - offset: allows setting the edge compensation in the range from
48 - offset-x: Same as offset, but applies only to the horizontal position.
52 - offset-y: Same as offset, but applies only to the vertical position.
/Documentation/media/uapi/v4l/
Dpixfmt-sdr-pcu20be.rst25 padded with 0. I value starts first and Q value starts at an offset
26 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
37 * - Offset:
53 * - start + offset:
58 * - start + offset + 4:

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