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/Documentation/devicetree/bindings/display/panel/
Dilitek,ili9322.txt1 Ilitek ILI9322 TFT panel driver with SPI control bus
4 streams that get adapted and scaled to the panel. The panel output has
9 - compatible: "dlink,dir-685-panel", "ilitek,ili9322"
10 (full system-specific compatible is always required to look up configuration)
11 - reg: address of the panel on the SPI bus
14 - vcc-supply: core voltage supply, see regulator/regulator.txt
15 - iovcc-supply: voltage supply for the interface input/output signals,
17 - vci-supply: voltage supply for analog parts, see regulator/regulator.txt
18 - reset-gpios: a GPIO spec for the reset pin, see gpio/gpio.txt
23 - pixelclk-active: see display/panel/display-timing.txt
[all …]
Dpanel-dpi.txt1 Generic MIPI DPI Panel
5 - compatible: "panel-dpi"
8 - label: a symbolic name for the panel
9 - enable-gpios: panel enable gpio
10 - reset-gpios: GPIO to control the RESET pin
11 - vcc-supply: phandle of regulator that will be used to enable power to the display
12 - backlight: phandle of the backlight device
15 - "panel-timing" containing video timings
16 (Documentation/devicetree/bindings/display/panel/display-timing.txt)
17 - Video port for DPI input
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Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
18 When referenced from panel device tree bindings the properties defined in this
19 document are defined as follows. The panel device tree bindings are
24 width-mm:
29 height-mm:
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Dsgd,gktw70sdae4se.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sgd,gktw70sdae4se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel
10 - Neil Armstrong <narmstrong@baylibre.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: lvds.yaml#
19 - const: sgd,gktw70sdae4se
20 - {} # panel-lvds, but not listed here to avoid false select
[all …]
Dolimex,lcd-olinuxino.txt1 Binding for Olimex Ltd. LCD-OLinuXino bridge panel.
5 - LCD-OLinuXino-4.3TS
6 - LCD-OLinuXino-5
7 - LCD-OLinuXino-7
8 - LCD-OLinuXino-10
10 The panel itself contains:
11 - AT24C16C EEPROM holding panel identification and timing requirements
12 - AR1021 resistive touch screen controller (optional)
13 - FT5x6 capacitive touch screnn controller (optional)
14 - GT911/GT928 capacitive touch screen controller (optional)
[all …]
Dmitsubishi,aa104xd12.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/mitsubishi,aa104xd12.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mitsubishi AA104XD12 10.4" XGA LVDS Display Panel
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: lvds.yaml#
19 - const: mitsubishi,aa104xd12
20 - {} # panel-lvds, but not listed here to avoid false select
[all …]
Dmitsubishi,aa121td01.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/mitsubishi,aa121td01.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mitsubishi AA121TD01 12.1" WXGA LVDS Display Panel
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: lvds.yaml#
19 - const: mitsubishi,aa121td01
20 - {} # panel-lvds, but not listed here to avoid false select
[all …]
Dsamsung,s6e8aa0.txt1 Samsung S6E8AA0 AMOLED LCD 5.3 inch panel
4 - compatible: "samsung,s6e8aa0"
5 - reg: the virtual channel number of a DSI peripheral
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel as described by [1]
12 - power-on-delay: delay after turning regulators on [ms]
13 - reset-delay: delay after reset sequence [ms]
14 - init-delay: delay after initialization sequence [ms]
[all …]
Dsamsung,ld9040.txt1 Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus
4 - compatible: "samsung,ld9040"
5 - reg: address of the panel on SPI bus
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel according to [1]
11 The panel must obey rules for SPI slave device specified in document [2].
14 - power-on-delay: delay after turning regulators on [ms]
15 - reset-delay: delay after reset sequence [ms]
[all …]
Dinnolux,ee101ia-01d.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/innolux,ee101ia-01d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel
10 - Heiko Stuebner <heiko.stuebner@bq.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: lvds.yaml#
19 - const: innolux,ee101ia-01d
20 - {} # panel-lvds, but not listed here to avoid false select
[all …]
Dlvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LVDS Display Panel
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
19 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
23 [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
[all …]
Ddisplay-timing.txt1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
14 timing subnode
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
[all …]
/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/Documentation/devicetree/bindings/display/exynos/
Dexynos7-decon.txt1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
8 - compatible: value should be "samsung,exynos7-decon";
10 - reg: physical base address and length of the DECON registers set.
12 - interrupts: should contain a list of all DECON IP block interrupts in the
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
20 - pinctrl-0: pin control group to be used for this controller.
22 - pinctrl-names: must contain a "default" entry.
24 - clocks: must include clock specifiers corresponding to entries in the
25 clock-names property.
27 - clock-names: list of clock names sorted in the same order as the clocks
[all …]
Dsamsung-fimd.txt1 Device-Tree bindings for Samsung SoC display controller (FIMD)
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
17 - reg: physical base address and length of the FIMD registers set.
[all …]
Dexynos_dp.txt2 the type of panel connected to it.
5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
[all …]
/Documentation/devicetree/bindings/display/
Drepaper.txt1 Pervasive Displays RePaper branded e-ink displays
4 - compatible: "pervasive,e1144cs021" for 1.44" display
9 - panel-on-gpios: Timing controller power control
10 - discharge-gpios: Discharge control
11 - reset-gpios: RESET pin
12 - busy-gpios: BUSY pin
15 - border-gpios: Border control
18 all mandatory properties described in ../spi/spi-bus.txt must be specified.
21 - pervasive,thermal-zone: name of thermometer's thermal zone
28 #thermal-sensor-cells = <0>;
[all …]
Darm,pl11x.txt7 - compatible: must be one of:
11 - reg: base address and size of the control registers block
13 - interrupt-names: either the single entry "combined" representing a
18 - interrupts: contains an interrupt specifier for each entry in
19 interrupt-names
21 - clock-names: should contain "clcdclk" and "apb_pclk"
23 - clocks: contains phandle and clock specifier pairs for the entries
24 in the clock-names property. See
25 Documentation/devicetree/bindings/clock/clock-bindings.txt
29 - memory-region: phandle to a node describing memory (see
[all …]
Dfsl,dcu.txt4 - compatible: Should be one of
5 * "fsl,ls1021a-dcu".
6 * "fsl,vf610-dcu".
8 - reg: Address and length of the register set for dcu.
9 - clocks: Handle to "dcu" and "pix" clock (in the order below)
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: Should be "dcu" and "pix"
13 See ../clocks/clock-bindings.txt for details.
14 - big-endian Boolean property, LS1021A DCU registers are big-endian.
15 - port Video port for the panel output
[all …]
Dcirrus,clps711x-fb.txt4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
21 compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
[all …]
Datmel,lcdc.txt2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 "atmel,at32ap-lcdc"
13 - reg : Should contain 1 register ranges(address and length).
[all …]
Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
[all …]
/Documentation/devicetree/bindings/display/imx/
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
[all …]
Dfsl,imx-fb.txt6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
20 - lcd-supply: Regulator for LCD supply voltage.
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
[all …]
/Documentation/media/v4l-drivers/
Ddavinci-vpbe.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------
28 -----------------------
49 board specific settings (specified in board-xxx-evm.c). This allows
59 at the port or LCD panel timings required. When external encoder/LCD panel
62 venc using non-standard timing mode.
64 Support LCD Panel displays using the VENC. For example to support a Logic
68 output name to board-xxx-evm.c). A table of timings for various LCDs
80 --------------
86 ----------
[all …]

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