| /Documentation/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
46 Package-related topology information in the kernel:
48 - cpuinfo_x86.x86_max_cores:
52 - cpuinfo_x86.x86_max_dies:
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
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| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
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| D | jcore,pit.txt | 1 J-Core Programmable Interval Timer and Clocksource
5 - compatible: Must be "jcore,pit".
7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
8 there should be one region per cpu, indexed by the sequential,
9 zero-based hardware cpu number.
11 - interrupts: An interrupt to assign for the timer. The actual pit
12 core is integrated with the aic and allows the timer interrupt
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| D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
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| D | samsung,exynos4210-mct.txt | 1 Samsung's Multi Core Timer (MCT)
3 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
4 global timer and CPU local timers. The global timer is a 64-bit free running
5 up-counter and can generate 4 interrupts when the counter reaches one of the
6 four preset counter values. The CPU local timers are 32-bit free running
7 down-counters and generate an interrupt when the counter expires. There is
12 - compatible: should be "samsung,exynos4210-mct".
13 (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
14 (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
16 - reg: base address of the mct controller and length of the address space
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | l4.txt | 6 - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
7 Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
8 Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
9 Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
10 Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
11 Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
12 Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
13 Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
14 Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
15 Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
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| /Documentation/cpu-freq/ |
| D | cpu-drivers.txt | 8 - information for developers -
23 ---------
26 1.2 Per-CPU Initialization
39 So, you just got a brand-new CPU / chipset with datasheets and want to
45 ------------------
49 chipset. If so, register a struct cpufreq_driver with the CPUfreq core
54 .name - The name of this driver.
56 .init - A pointer to the per-policy initialization function.
58 .verify - A pointer to a "verification" function.
60 .setpolicy _or_ .fast_switch _or_ .target _or_ .target_index - See
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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| /Documentation/hwmon/ |
| D | coretemp.rst | 5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
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| /Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
26 - reg : address + size pairs describing the PMIC arb register sets; order must
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| /Documentation/devicetree/bindings/firmware/ |
| D | qcom,scm.txt | 9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-msm8660"
14 * "qcom,scm-msm8916"
15 * "qcom,scm-msm8960"
16 * "qcom,scm-msm8974"
17 * "qcom,scm-msm8996"
18 * "qcom,scm-msm8998"
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-lpspi.txt | 4 - compatible :
5 - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc
6 - "fsl,imx8qxp-spi" for LPSPI compatible with the one integrated on i.MX8QXP soc
7 - reg : address and length of the lpspi master registers
8 - interrupt-parent : core interrupt controller
9 - interrupts : lpspi interrupt
10 - clocks : lpspi clock specifier. Its number and order need to correspond to the
11 value in clock-names.
12 - clock-names : Corresponding to per clock and ipg clock in "clocks"
13 respectively. In i.MX7ULP, it only has per clk, so use CLK_DUMMY
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| D | spi-sifive.txt | 2 ------------------------------------------
5 - compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>".
7 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
10 Please refer to sifive-blocks-ip-versioning.txt for details
11 - reg : Physical base address and size of SPI registers map
13 - interrupts : Must contain one entry
14 - interrupt-parent : Must be core interrupt controller
15 - clocks : Must reference the frequency given to the controller
16 - #address-cells : Must be '1', indicating which CS to use
17 - #size-cells : Must be '0'
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | jcore,aic.txt | 1 J-Core Advanced Interrupt Controller
5 - compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
7 the "aic2" core with 64 interrupts.
9 - reg: Memory region(s) for configuration. For SMP, there should be one
10 region per cpu, indexed by the sequential, zero-based hardware cpu
13 - interrupt-controller: Identifies the node as an interrupt controller
15 - #interrupt-cells: Specifies the number of cells needed to encode an
21 aic: interrupt-controller@200 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
|
| /Documentation/usb/ |
| D | dwc3.rst | 11 - Convert interrupt handler to per-ep-thread-irq
13 As it turns out some DWC3-commands ~1ms to complete. Currently we spin
18 - dwc core implements a demultiplexing irq chip for interrupts per
20 to the device. If MSI provides per-endpoint interrupt this dummy
22 - interrupts are requested / allocated on usb_ep_enable() and removed on
25 - dwc3_send_gadget_ep_cmd() will sleep in wait_for_completion_timeout()
27 - the interrupt handler is split into the following pieces:
29 - primary handler of the device
34 - threaded handler of the device
37 - primary handler of the EP-interrupt
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,keystone-rproc.txt | 4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
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| /Documentation/driver-api/ |
| D | men-chameleon-bus.rst | 30 ----------------------
37 -----------------------------------------
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
56 - the parser for the Chameleon table.
59 -----------------
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| D | sm501.rst | 14 Core chapter
15 ----
17 The core driver in drivers/mfd provides common services for the
22 The core registers drivers for both PCI and generic bus based
25 On detection of a device, the core initialises the chip (which may
29 The core re-uses the platform device system as the platform device
31 need to create a new bus-type and the associated code to go with it.
35 ---------
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
23 in the system and map to the hierarchy level "core" above.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
32 The cpu nodes, as per bindings defined in [4], represent the devices that
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 2 -------------------------------------
8 Each video IP core is represented by an AMBA bus child node in the device
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
23 core is described in the IP core bindings documentation.
25 - xlnx,video-width: This property qualifies the video format with the sample
26 width expressed as a number of bits per pixel component. All components must
29 - xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-mediatek.txt | 4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.
10 - "mediatek,mt8516-pwm": found on mt8516 SoC.
11 - reg: physical base address and length of the controller's registers.
12 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
14 - clocks: phandle and clock specifier of the PWM reference clock.
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| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3
24 - arm,cortex-a73-pmu
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
7 DSS Core
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-dsp-keystone.txt | 4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
8 - 8 for C66x CorePacx CPUs 0-7
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
21 - gpio-controller: Marks the device node as a gpio controller.
22 - #gpio-cells: Should be 2.
29 compatible = "ti,keystone-dsp-gpio";
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