Searched full:peripherals (Results 1 – 25 of 92) sorted by relevance
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| /Documentation/devicetree/bindings/display/ |
| D | mipi-dsi-bus.txt | 5 communication between a host and up to four peripherals. This document will
13 peripherals on that bus.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
42 Peripherals with DSI as control bus, or no control bus
45 Peripherals with the DSI bus as the primary control bus, or peripherals with
48 DSI peripherals, but individual bindings may want to define additional,
55 Some DSI peripherals respond to more than a single virtual channel. In that
64 Peripherals with a different control bus
67 There are peripherals that have I2C/SPI (or some other non-DSI bus) as the
69 path). Connections between such peripherals and a DSI host can be represented
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| /Documentation/devicetree/bindings/misc/ |
| D | ge-achc.txt | 3 A device which handles data aquisition from compatible USB based peripherals.
6 Note: This device does not expose the peripherals as USB devices.
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| D | lwn-bk4.txt | 4 peripherals.
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| /Documentation/devicetree/bindings/arm/ |
| D | primecell.yaml | 7 title: ARM Primecell Peripherals
13 ARM, Ltd. Primecell peripherals have a standard id register that can be used to
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| D | vexpress.txt | 6 peripherals. Processor and RAM "live" on the tiles.
132 - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
137 with the original CoreTile Express A9x4) with peripherals on CS7.
139 Motherboard .dtsi files provide a set of labelled peripherals that
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| /Documentation/devicetree/bindings/clock/ |
| D | brcm,bcm2835-aux-clock.txt | 6 The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
7 area controlling clock gating to the peripherals, and providing an IRQ
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| D | qcom,spmi-clkdiv.txt | 19 Definition: base address of CLKDIV peripherals.
24 Definition: number of CLKDIV peripherals.
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| D | pistachio-clock.txt | 21 co-processor), audio, and several peripherals.
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
75 resets for various peripherals. It also contains miscellaneous peripheral
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-spmi-temp-alarm.txt | 3 QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
4 that utilize the Qualcomm SPMI implementation. These peripherals provide an
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| /Documentation/devicetree/bindings/bus/ |
| D | ts-nbus.txt | 3 The NBUS is a bus used to interface with peripherals in the Technologic
20 The NBUS node can contain zero or more child nodes representing peripherals
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| D | ti,da850-mstpri.txt | 5 peripherals classified as masters.
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| /Documentation/arm/samsung-s3c24xx/ |
| D | smdk2440.rst | 33 Peripherals chapter
36 There is no current support for any of the extra peripherals on the
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 4 The CE4100 SoC uses for in core peripherals the following compatible
44 This node describes the in-core peripherals. Required property:
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| /Documentation/devicetree/ |
| D | overlay-notes.txt | 29 /* On chip peripherals */
31 /* peripherals that are always instantiated */
67 /* On chip peripherals */
69 /* peripherals that are always instantiated */
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| /Documentation/devicetree/bindings/mfd/ |
| D | ti-keystone-devctrl.txt | 4 the status of its peripherals. This node is intended to allow access to
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| D | qcom,tcsr.txt | 4 functions for their peripherals. This node is intended to allow access to these
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| D | max77802.txt | 5 up application processors and peripherals, a 2-channel 32kHz clock outputs,
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 56 - RFBI controlled peripherals
74 - DSI controlled peripherals
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| D | ti,omap4-dss.txt | 56 - RFBI controlled peripherals
93 - DSI controlled peripherals
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| /Documentation/devicetree/bindings/soc/zte/ |
| D | pd-2967xx.txt | 4 to gate power to one or more peripherals on the processor.
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| /Documentation/devicetree/bindings/dma/ |
| D | st_fdma.txt | 15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
31 reg-names = "slimcore", "dmem", "peripherals", "imem";
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7d-pinctrl.txt | 22 Peripherals using pads from iomuxc-lpsr support low state retention power
56 While iomuxc-lpsr is intended to be used by dedicated peripherals to take
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 22 - num-perips: Number of waking peripherals.
67 // Three peripherals are connected.
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | hsta.txt | 7 transfer between memory and system peripherals as well as support for
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| /Documentation/devicetree/bindings/arm/ux500/ |
| D | power_domain.txt | 4 more peripherals on the SOC.
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