Searched full:phase (Results 1 – 25 of 124) sorted by relevance
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| /Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
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| D | hi3798cv200-dw-mshc.txt | 19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
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| D | rockchip-dw-mshc.txt | 33 * rockchip,default-sample-phase: The default phase to set ciu-sample at
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| /Documentation/networking/ |
| D | cops.txt | 52 dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
53 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
56 eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
57 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
61 lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
62 lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
63 eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
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| D | ltpc.txt | 47 dummy -seed -phase 2 -net 2000 -addr 2000.26 -zone "1033"
48 lt0 -seed -phase 1 -net 1033 -addr 1033.27 -zone "1033"
62 lt0 -phase 1
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| /Documentation/devicetree/bindings/sound/ |
| D | max98504.txt | 20 applied during the "attack hold" and "timed hold" phase, the value must be
22 - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms,
24 - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms,
26 - maxim,brownout-release-rate-ms - the brownout release phase step time in ms,
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | sky81452-backlight.txt | 14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
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| /Documentation/driver-api/pm/ |
| D | devices.rst | 242 always go together, and both are multi-phase operations.
279 sleep states and the hibernation state ("suspend-to-disk"). Each phase involves
280 executing callbacks for every device before the next phase begins. Not all
293 rules are used to determine which callback to execute in the given phase:
326 1. The ``prepare`` phase is meant to prevent races by preventing new
331 suspend-related phases, during the ``prepare`` phase the device
397 4. The ``suspend_noirq`` phase occurs after IRQ handlers have been disabled,
406 an error during the suspend phase by fielding a shared interrupt
436 generally means undoing the actions of the ``suspend_noirq`` phase. If
450 the preceding ``suspend_late`` phase.
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| /Documentation/devicetree/bindings/mfd/ |
| D | axp20x.txt | 126 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
127 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
129 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
130 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
153 DCDCA : DC-DC buck : vina-supply : poly-phase capable
154 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
155 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
156 DCDCD : DC-DC buck : vind-supply : poly-phase capable
157 DCDCE : DC-DC buck : vine-supply : poly-phase capable
170 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
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| D | sky81452.txt | 24 skyworks,phase-shift;
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| /Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 61 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
65 - 0: No phase shift.
66 - 1: 90 degree phase shift sampling.
67 - 2: 180 degree phase shift sampling.
68 - 3: 270 degree phase shift sampling.
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | ad5755.txt | 23 - adi,dc-dc-phase:
24 Valid values for DC DC Phase control is:
31 clock 90 degrees out of phase from each other.
97 adi,dc-dc-phase = <0>;
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adf4350.txt | 22 - adi,phase-detector-polarity-positive-enable: Enables positive phase
54 2: Phase resync enable
82 adi,phase-detector-polarity-positive-enable;
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| /Documentation/admin-guide/mm/ |
| D | memory-hotplug.rst | 47 1) Physical Memory Hotplug phase
48 2) Logical Memory Hotplug phase.
50 The First phase is to communicate hardware/firmware and make/erase
51 environment for hotplugged memory. Basically, this phase is necessary
52 for the purpose (B), but this is good phase for communication between
59 this phase is triggered automatically. ACPI can notify this event. If not,
63 Logical Memory Hotplug phase is to change memory state into
65 changed by this phase. The kernel makes all memory in it as free pages
68 In this document, this phase is described as online/offline.
70 Logical Memory Hotplug phase is triggered by write of sysfs file by system
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| /Documentation/media/v4l-drivers/ |
| D | radiotrack.rst | 105 0 0 "zero" bit phase 1
106 0 1 "zero" bit phase 2
107 1 0 "one" bit phase 1
108 1 1 "one" bit phase 2
161 disable, "zero" bit phase 1, tuner adjust)
163 disable, "zero" bit phase 2, tuner adjust)
166 disable, "one" bit phase 1, tuner adjust)
168 disable, "one" bit phase 2, tuner adjust)
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| /Documentation/devicetree/bindings/mtd/ |
| D | amlogic,meson-nand.txt | 17 "rx" - rx clock phase
18 "tx" - tx clock phase
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| D | davinci-nand.txt | 28 phase. These offset will be added to the base
34 phase. These offset will be added to the base
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| /Documentation/cpu-freq/ |
| D | core.txt | 62 The phase is specified in the second argument to the notifier. The phase is
78 The second argument specifies the phase - CPUFREQ_PRECHANGE or
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| /Documentation/power/ |
| D | suspend-and-interrupts.rst | 13 suspend after the "late" phase of suspending devices (that is, after all of the
17 The rationale for doing so is that after the "late" phase of device suspend
26 of suspend_device_irqs(), along with the "noirq" phase of device suspend and
29 Device IRQs are re-enabled during system resume, right before the "early" phase
101 interrupts right after the "noirq" phase of suspending devices.
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| /Documentation/devicetree/bindings/power/supply/ |
| D | bq25890.txt | 13 constant-voltage phase drops below this value (in uA);
15 phase (in uA);
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| D | battery.txt | 22 - precharge-current-microamp: current for pre-charge phase
23 - charge-term-current-microamp: current for charge termination phase
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| /Documentation/devicetree/bindings/display/ |
| D | ssd1307fb.txt | 26 - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
27 - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
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| /Documentation/scsi/ |
| D | ChangeLog.sym53c8xx | 59 not requires extra cycles in DT DATA OUT phase.
162 data phase. Changes based on those made in the
318 in DATA IN phase with WIDE transfer when the byte count gets odd).
324 transfer, whatever a SWIDE is present (OVERRUN in DATA IN phase)
325 or the SODL is full (UNDERRUN in DATA out phase).
341 to testing for a PHASE. SYMBIOS say this feature is working fine.
447 - Fix for big-endian in phase mismatch handling. (Michal Jaegermann)
465 - Reduce a bit the number of IO register reads for phase mismatch
472 with all features enabled including the phase mismatch handling
526 - Print out some message if phase mismatch is handled from SCRIPTS.
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| /Documentation/devicetree/bindings/regulator/ |
| D | da9210.txt | 1 * Dialog Semiconductor DA9210 Multi-phase 12A DCDC BUCK Converter
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