Searched +full:phy +full:- +full:mode (Results 1 – 25 of 150) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
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| D | ti-phy-gmii-sel.txt | 1 CPSW Port's Interface Mode Selection PHY Tree Bindings
2 -----------------------------------------------
6 The interface mode is selected by configuring the MII mode selection register(s)
10 +--------------+
11 +-------------------------------+ |SCM |
12 | CPSW | | +---------+ |
13 | +--------------------------------+gmii_sel | |
14 | | | | +---------+ |
15 | +----v---+ +--------+ | +--------------+
16 | |Port 1..<--+-->GMII/MII<------->
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| D | brcm-sata-phy.txt | 1 * Broadcom SATA3 PHY
4 - compatible: should be one or more of
5 "brcm,bcm7425-sata-phy"
6 "brcm,bcm7445-sata-phy"
7 "brcm,iproc-ns2-sata-phy"
8 "brcm,iproc-nsp-sata-phy"
9 "brcm,phy-sata3"
10 "brcm,iproc-sr-sata-phy"
11 "brcm,bcm63138-sata-phy"
12 - address-cells: should be 1
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| D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| D | meson-gxl-usb3-phy.txt | 1 * Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
4 - compatible: Should be "amlogic,meson-gxl-usb3-phy"
5 - #phys-cells: must be 0 (see phy-bindings.txt in this directory)
6 - reg: The base address and length of the registers
7 - interrupts: the interrupt specifier for the OTG detection
8 - clocks: phandles to the clocks for
9 - the USB3 PHY
10 - and peripheral mode/OTG detection
11 - clock-names: must contain "phy" and "peripheral"
12 - resets: phandle to the reset lines for:
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| D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
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| D | phy-mapphone-mdm6600.txt | 1 Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
4 - compatible Must be "motorola,mapphone-mdm6600"
5 - enable-gpios GPIO to enable the USB PHY
6 - power-gpios GPIO to power on the device
7 - reset-gpios GPIO to reset the device
8 - motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
9 normal mode versus USB flashing mode
10 - motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
11 - motorola,status-gpios Three GPIOs to read the power state of the MDM6600
15 usb-phy {
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| D | brcm,brcmstb-usb-phy.txt | 1 Broadcom STB USB PHY
4 - compatible: brcm,brcmstb-usb-phy
5 - reg: two offset and length pairs.
7 registers used for general control of the PHY.
10 - #phy-cells: Shall be 1 as it expects one argument for setting
11 the type of the PHY. Possible values are:
12 - PHY_TYPE_USB2 for USB1.1/2.0 PHY
13 - PHY_TYPE_USB3 for USB3.x PHY
16 - clocks : clock phandles.
17 - clock-names: String, clock name.
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| D | phy-cpcap-usb.txt | 1 Motorola CPCAP PMIC USB PHY binding
4 compatible: Shall be either "motorola,cpcap-usb-phy" or
5 "motorola,mapphone-cpcap-usb-phy"
6 #phy-cells: Shall be 0
7 interrupts: CPCAP PMIC interrupts used by the USB PHY
8 interrupt-names: Interrupt names
9 io-channels: IIO ADC channels used by the USB PHY
10 io-channel-names: IIO ADC channel names
11 vusb-supply: Regulator for the PHY
14 pinctrl: Optional alternate pin modes for the PHY
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
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| D | micrel.txt | 1 Micrel PHY properties.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
20 See the respective PHY datasheet for the mode values.
22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
26 than 50 MHz clock mode.
28 Note that this option in only needed for certain PHY revisions with a
29 non-standard, inverted function of this configuration bit.
30 Specifically, a clock reference ("rmii-ref" below) is always needed to
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| D | socionext,uniphier-ave4.txt | 7 - compatible: Should be
8 - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
9 - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
10 - "socionext,uniphier-ld11-ave4" : for LD11 SoC
11 - "socionext,uniphier-ld20-ave4" : for LD20 SoC
12 - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC
13 - reg: Address where registers are mapped and size of region.
14 - interrupts: Should contain the MAC interrupt.
15 - phy-mode: See ethernet.txt in the same directory. Allow to choose
16 "rgmii", "rmii", "mii", or "internal" according to the PHY.
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| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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| D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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| D | nixge.txt | 4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
11 "ctrl": MDIO and PHY control and status region
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
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| D | hisilicon-hip04-net.txt | 6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
28 - compatible: "hisilicon,hip04-ppe", "syscon".
29 - reg: address and length of the register set for the device.
36 - compatible: should be "hisilicon,mdio".
37 - Inherits from MDIO bus node binding [2]
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| D | emac_rockchip.txt | 4 - compatible: should be "rockchip,<name>-emac"
5 "rockchip,rk3036-emac": found on RK3036 SoCs
6 "rockchip,rk3066-emac": found on RK3066 SoCs
7 "rockchip,rk3188-emac": found on RK3188 SoCs
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain the EMAC interrupts
10 - rockchip,grf: phandle to the syscon grf used to control speed and mode
12 - phy: see ethernet.txt file in the same directory.
13 - phy-mode: see ethernet.txt file in the same directory.
16 - phy-supply: phandle to a regulator if the PHY needs one
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| D | smsc-lan87xx.txt | 1 SMSC LAN87xx Ethernet PHY
8 - smsc,disable-energy-detect:
9 If set, do not enable energy detect mode for the SMSC phy.
10 default: enable energy detect mode
13 smsc phy with disabled energy detect mode on an am335x based board.
15 pinctrl-names = "default", "sleep";
16 pinctrl-0 = <&davinci_mdio_default>;
17 pinctrl-1 = <&davinci_mdio_sleep>;
19 ethernetphy0: ethernet-phy@0 {
21 smsc,disable-energy-detect;
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| /Documentation/devicetree/bindings/usb/ |
| D | dwc2.txt | 2 -----------------------------------------------------
5 - compatible : One of:
6 - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
7 - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
8 - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
9 - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
10 - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
11 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
12 - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
13 - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
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| D | omap-usb.txt | 4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
8 - #address-cells: Must be 1.
9 - #size-cells: Must be 0.
10 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
11 on multi-chip module belong to MT7623A has or the remotely standalone
16 - core-supply: Phandle to the regulator node necessary for the core power.
17 - io-supply: Phandle to the regulator node necessary for the I/O power.
18 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
23 - reset-gpios: Should be a gpio specifier for a reset line.
27 - resets : Phandle pointing to the system reset controller with
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| D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
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| D | lantiq-gswip.txt | 6 - compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
8 - reg : memory range of the GSWIP core registers
17 - compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
25 - compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
26 "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
27 "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
30 - lantiq,rcu : reference to the rcu syscon
35 - reg : Offset of the GPHY firmware register in the RCU
37 - resets : list of resets of the embedded GPHY
38 - reset-names : list of names of the resets
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| /Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 7 clock and PHY.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
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