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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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Dallwinner,sunxi-pinctrl.txt6 the pins includes drive strength and pull-up.
9 - compatible: Should be one of the following (depending on your SoC):
10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31s-pinctrl"
15 "allwinner,sun6i-a31-r-pinctrl"
16 "allwinner,sun7i-a20-pinctrl"
17 "allwinner,sun8i-a23-pinctrl"
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Dmarvell,mvebu-pinctrl.txt1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
8 common pinctrl bindings used by client devices, including the meaning of the
15 Required properties for pinctrl driver:
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
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Dmeson,pinctrl.txt4 - compatible: one of "amlogic,meson8-cbus-pinctrl"
5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8m2-cbus-pinctrl"
7 "amlogic,meson8-aobus-pinctrl"
8 "amlogic,meson8b-aobus-pinctrl"
9 "amlogic,meson8m2-aobus-pinctrl"
10 "amlogic,meson-gxbb-periphs-pinctrl"
11 "amlogic,meson-gxbb-aobus-pinctrl"
12 "amlogic,meson-gxl-periphs-pinctrl"
13 "amlogic,meson-gxl-aobus-pinctrl"
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Dpinctrl-mt65xx.txt6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
14 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
15 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
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Dsocionext,uniphier-pinctrl.txt4 - compatible: should be one of the following:
5 "socionext,uniphier-ld4-pinctrl" - for LD4 SoC
6 "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC
7 "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC
8 "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC
9 "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC
10 "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC
11 "socionext,uniphier-ld11-pinctrl" - for LD11 SoC
12 "socionext,uniphier-ld20-pinctrl" - for LD20 SoC
13 "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC
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Dpinctrl-atlas7.txt4 - compatible : "sirf,atlas7-ioc"
5 - reg : Address range of the pinctrl registers
7 For example, pinctrl might have properties like the following:
8 pinctrl: ioc@18880000 {
9 compatible = "sirf,atlas7-ioc";
10 reg = <0x18880000 0x1000>;
12 a_ac97_pmx: ac97@0 {
21 sd2_pmx: sd2@0 {
31 sample0_cfg: sample0@0 {
34 bias-pull-up;
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Dingenic,pinctrl.txt3 Please refer to pinctrl-bindings.txt in this directory for details of the
4 common pinctrl bindings used by client devices, including the meaning of the
11 which the pin is associated and N is an integer from 0 to 31 identifying the
19 --------------------
21 - compatible: One of:
22 - "ingenic,jz4740-pinctrl"
23 - "ingenic,jz4725b-pinctrl"
24 - "ingenic,jz4760-pinctrl"
25 - "ingenic,jz4760b-pinctrl"
26 - "ingenic,jz4770-pinctrl"
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Drockchip,pinctrl.txt6 muxing options with option 0 being the use as a GPIO.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
9 common pinctrl bindings used by client devices, including the meaning of the
16 settings such as pull-up, etc.
19 defined as gpio sub-nodes of the pinmux controller.
22 - compatible: should be
23 "rockchip,px30-pinctrl": for Rockchip PX30
24 "rockchip,rv1108-pinctrl": for Rockchip RV1108
25 "rockchip,rk2928-pinctrl": for Rockchip RK2928
26 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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Dcnxt,cx92755-pinctrl.txt11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
21 pinctrl: pinctrl@f0000e20 {
22 compatible = "cnxt,cx92755-pinctrl";
23 reg = <0xf0000e20 0x100>;
24 gpio-controller;
25 #gpio-cells = <2>;
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Dpinctrl-rk805.txt5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
6 for details of the common pinctrl bindings used by client devices,
10 --------------------------
13 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
14 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
15 <pinctrl-bindings.txt>.
17 The pin configurations are defined as child of the pinctrl states node. Each
18 sub-node have following properties:
21 ------------------
22 - #gpio-cells: Should be two. The first cell is the pin number and the
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Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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Daxis,artpec6-pinctrl.txt1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
8 A pinctrl node should contain at least one subnode representing the pinctrl
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
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Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl",
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/Documentation/devicetree/bindings/i2c/
Di2c-mux-pinctrl.txt1 Pinctrl-based I2C Bus Mux
5 using the pinctrl device tree bindings.
7 +-----+ +-----+
9 +------------------------+ +-----+ +-----+
11 | /----|------+--------+
12 | +---+ +------+ | child bus A, on first set of pins
13 | |I2C|---|Pinmux| |
14 | +---+ +------+ | child bus B, on second set of pins
15 | \----|------+--------+--------+
17 +------------------------+ +-----+ +-----+ +-----+
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/Documentation/devicetree/bindings/input/touchscreen/
Dcolibri-vf50-ts.txt4 - compatible must be toradex,vf50-touchscreen
5 - io-channels: adc channels being used by the Colibri VF50 module
6 - xp-gpios: FET gate driver for input of X+
7 - xm-gpios: FET gate driver for input of X-
8 - yp-gpios: FET gate driver for input of Y+
9 - ym-gpios: FET gate driver for input of Y-
10 - interrupts: pen irq interrupt for touch detection
11 - pinctrl-names: "idle", "default", "gpios"
12 - pinctrl-0: pinctrl node for pen/touch detection state pinmux
13 - pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux
[all …]
Dsis_i2c.txt4 - compatible: must be "sis,9200-ts"
5 - reg: i2c slave address
6 - interrupts: touch controller interrupt (see interrupt
7 binding [0])
10 - pinctrl-names: should be "default" (see pinctrl binding [1]).
11 - pinctrl-0: a phandle pointing to the pin settings for the
12 device (see pinctrl binding [1]).
13 - attn-gpios: the gpio pin used as attention line
14 - reset-gpios: the gpio pin used to reset the controller
15 - wakeup-source: touchscreen can be used as a wakeup source
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/Documentation/devicetree/bindings/serial/
Dmicrochip,pic32-uart.txt4 - compatible: Should be "microchip,pic32mzda-uart"
5 - reg: Should contain registers location and length
6 - interrupts: Should contain interrupt
7 - clocks: Phandle to the clock.
8 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - pinctrl-names: A pinctrl state names "default" must be defined.
10 - pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
11 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
14 - cts-gpios: CTS pin for UART
18 compatible = "microchip,pic32mzda-uart";
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/Documentation/devicetree/bindings/net/
Dmicrochip,enc28j60.txt9 - compatible: Should be "microchip,enc28j60"
10 - reg: Specify the SPI chip select the ENC28J60 is wired to
11 - interrupts: Specify the interrupt index within the interrupt controller (referred
12 to above in interrupt-parent) and interrupt type. The ENC28J60 natively
15 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
16 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
17 see also generic and your platform specific pinctrl binding
21 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
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/Documentation/devicetree/bindings/sound/
Drockchip,pdm.txt5 - compatible: "rockchip,pdm"
6 - "rockchip,px30-pdm"
7 - "rockchip,rk1808-pdm"
8 - "rockchip,rk3308-pdm"
9 - reg: physical base address of the controller and length of memory mapped
11 - dmas: DMA specifiers for rx dma. See the DMA client binding,
13 - dma-names: should include "rx".
14 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
15 - clock-names: should contain following:
16 - "pdm_hclk": clock for PDM BUS
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/Documentation/devicetree/bindings/input/
Dimx-keypad.txt3 The KPP is designed to interface with a keypad matrix with 2-point contact
4 or 3-point contact keys. The KPP is designed to simplify the software task
9 - compatible: Should be "fsl,<soc>-kpp".
11 - reg: Physical base address of the KPP and length of memory mapped
14 - interrupts: The KPP interrupt number to the CPU(s).
16 - clocks: The clock provided by the SoC to the KPP. Some SoCs use dummy
20 - pinctrl-names: The definition can be found at
21 pinctrl/pinctrl-bindings.txt.
23 - pinctrl-0: The definition can be found at
24 pinctrl/pinctrl-bindings.txt.
[all …]
/Documentation/devicetree/bindings/mmc/
Dmicrochip,sdhci-pic32.txt4 and the properties used by the sdhci-pic32 driver.
7 - compatible: Should be "microchip,pic32mzda-sdhci"
8 - interrupts: Should contain interrupt
9 - clock-names: Should be "base_clk", "sys_clk".
10 See: Documentation/devicetree/bindings/resource-names.txt
11 - clocks: Phandle to the clock.
12 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - pinctrl-names: A pinctrl state names "default" must be defined.
14 - pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
15 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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/Documentation/devicetree/bindings/phy/
Dphy-cpcap-usb.txt4 compatible: Shall be either "motorola,cpcap-usb-phy" or
5 "motorola,mapphone-cpcap-usb-phy"
6 #phy-cells: Shall be 0
8 interrupt-names: Interrupt names
9 io-channels: IIO ADC channels used by the USB PHY
10 io-channel-names: IIO ADC channel names
11 vusb-supply: Regulator for the PHY
14 pinctrl: Optional alternate pin modes for the PHY
15 pinctrl-names: Names for optional pin modes
16 mode-gpios: Optional GPIOs for configuring alternate modes
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/Documentation/devicetree/bindings/pwm/
Dpwm-stm32.txt3 Must be a sub-node of an STM32 Timers device tree node.
4 See ../mfd/stm32-timers.txt for details about the parent node.
7 - compatible: Must be "st,stm32-pwm".
8 - pinctrl-names: Set to "default".
9 - pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
10 For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
11 - #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
15 - st,breakinput: One or two <index level filter> to describe break input configurations.
16 "index" indicates on which break input (0 or 1) the configuration
18 "level" gives the active level (0=low or 1=high) of the input signal
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