Searched +full:pinctrl +full:- +full:names (Results 1 – 25 of 325) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | rockchip,pdm.txt | 5 - compatible: "rockchip,pdm"
6 - "rockchip,px30-pdm"
7 - "rockchip,rk1808-pdm"
8 - "rockchip,rk3308-pdm"
9 - reg: physical base address of the controller and length of memory mapped
11 - dmas: DMA specifiers for rx dma. See the DMA client binding,
13 - dma-names: should include "rx".
14 - clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
15 - clock-names: should contain following:
16 - "pdm_hclk": clock for PDM BUS
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| D | qcom,lpass-cpu.txt | 3 This node models the Qualcomm Technologies Low-Power Audio SubSystem (LPASS).
7 - compatible : "qcom,lpass-cpu" or "qcom,apq8016-lpass-cpu"
8 - clocks : Must contain an entry for each entry in clock-names.
9 - clock-names : A list which must include the following entries:
10 * "ahbix-clk"
11 * "mi2s-osr-clk"
12 * "mi2s-bit-clk"
13 : required clocks for "qcom,lpass-cpu-apq8016"
14 * "ahbix-clk"
15 * "mi2s-bit-clk0"
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| D | sirf-usp.txt | 4 - compatible: "sirf,prima2-usp-pcm"
5 - reg: Base address and size entries:
6 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
7 - dma-names: Identifier string for each DMA request line in the dmas property.
13 - clocks: USP controller clock source
14 - pinctrl-names: Must contain a "default" entry.
15 - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
19 compatible = "sirf,prima2-usp-pcm";
23 dma-names = "rx", "tx";
24 pinctrl-names = "default";
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-cpcap-usb.txt | 4 compatible: Shall be either "motorola,cpcap-usb-phy" or
5 "motorola,mapphone-cpcap-usb-phy"
6 #phy-cells: Shall be 0
8 interrupt-names: Interrupt names
9 io-channels: IIO ADC channels used by the USB PHY
10 io-channel-names: IIO ADC channel names
11 vusb-supply: Regulator for the PHY
14 pinctrl: Optional alternate pin modes for the PHY
15 pinctrl-names: Names for optional pin modes
16 mode-gpios: Optional GPIOs for configuring alternate modes
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| D | qcom,usb-hsic-phy.txt | 5 - compatible:
8 Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
11 "qcom,usb-hsic-phy-mdm9615"
12 "qcom,usb-hsic-phy-msm8974"
14 - #phy-cells:
19 - clocks:
21 Value type: <prop-encoded-array>
25 - clock-names:
30 - pinctrl-names:
35 - pinctrl-0:
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| /Documentation/devicetree/bindings/mmc/ |
| D | microchip,sdhci-pic32.txt | 4 and the properties used by the sdhci-pic32 driver.
7 - compatible: Should be "microchip,pic32mzda-sdhci"
8 - interrupts: Should contain interrupt
9 - clock-names: Should be "base_clk", "sys_clk".
10 See: Documentation/devicetree/bindings/resource-names.txt
11 - clocks: Phandle to the clock.
12 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - pinctrl-names: A pinctrl state names "default" must be defined.
14 - pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
15 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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| D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-pinctrl.txt | 1 Pinctrl-based I2C Bus Mux
5 using the pinctrl device tree bindings.
7 +-----+ +-----+
9 +------------------------+ +-----+ +-----+
11 | /----|------+--------+
12 | +---+ +------+ | child bus A, on first set of pins
13 | |I2C|---|Pinmux| |
14 | +---+ +------+ | child bus B, on second set of pins
15 | \----|------+--------+--------+
17 +------------------------+ +-----+ +-----+ +-----+
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| /Documentation/devicetree/bindings/usb/ |
| D | ehci-st.txt | 4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - phys : phandle for the PHY device
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| D | dwc3-st.txt | 3 This file documents the parameters for the dwc3-st driver.
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
16 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
19 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
22 - pinctl-names : A pinctrl state named "default" must be defined
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| /Documentation/devicetree/bindings/thermal/ |
| D | rockchip-thermal.txt | 4 - compatible : should be "rockchip,<name>-tsadc"
5 "rockchip,px30-tsadc": found on PX30 SoCs
6 "rockchip,rv1108-tsadc": found on RV1108 SoCs
7 "rockchip,rk3228-tsadc": found on RK3228 SoCs
8 "rockchip,rk3288-tsadc": found on RK3288 SoCs
9 "rockchip,rk3328-tsadc": found on RK3328 SoCs
10 "rockchip,rk3368-tsadc": found on RK3368 SoCs
11 "rockchip,rk3399-tsadc": found on RK3399 SoCs
12 - reg : physical base address of the controller and length of memory mapped
14 - interrupts : The interrupt number to the cpu. The interrupt specifier format
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| /Documentation/devicetree/bindings/pwm/ |
| D | nvidia,tegra20-pwm.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - reg: physical base address and length of the controller's registers
13 - #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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| D | pwm-mtk-disp.txt | 4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
8 - reg: physical base address and length of the controller's registers.
9 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - clock-names: must contain the following:
13 - "main": clock used to generate PWM signals.
14 - "mm": sync signals from the modules of mmsys.
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| D | pwm-mediatek.txt | 4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt7622-pwm": found on mt7622 SoC.
7 - "mediatek,mt7623-pwm": found on mt7623 SoC.
8 - "mediatek,mt7628-pwm": found on mt7628 SoC.
9 - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.
10 - "mediatek,mt8516-pwm": found on mt8516 SoC.
11 - reg: physical base address and length of the controller's registers.
12 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
14 - clocks: phandle and clock specifier of the PWM reference clock.
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| /Documentation/devicetree/bindings/media/ |
| D | stih407-c8sectpfe.txt | 14 - compatible : Should be "stih407-c8sectpfe"
16 - reg : Address and length of register sets for each device in
17 "reg-names"
19 - reg-names : The names of the register addresses corresponding to the
21 - c8sectpfe: c8sectpfe registers
22 - c8sectpfe-ram: c8sectpfe internal sram
24 - clocks : phandle list of c8sectpfe clocks
25 - clock-names : should be "c8sectpfe"
26 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
28 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
8 common pinctrl bindings used by client devices, including the meaning of the
15 Required properties for pinctrl driver:
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
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| D | meson,pinctrl.txt | 4 - compatible: one of "amlogic,meson8-cbus-pinctrl"
5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8m2-cbus-pinctrl"
7 "amlogic,meson8-aobus-pinctrl"
8 "amlogic,meson8b-aobus-pinctrl"
9 "amlogic,meson8m2-aobus-pinctrl"
10 "amlogic,meson-gxbb-periphs-pinctrl"
11 "amlogic,meson-gxbb-aobus-pinctrl"
12 "amlogic,meson-gxl-periphs-pinctrl"
13 "amlogic,meson-gxl-aobus-pinctrl"
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| /Documentation/devicetree/bindings/serial/ |
| D | microchip,pic32-uart.txt | 4 - compatible: Should be "microchip,pic32mzda-uart"
5 - reg: Should contain registers location and length
6 - interrupts: Should contain interrupt
7 - clocks: Phandle to the clock.
8 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - pinctrl-names: A pinctrl state names "default" must be defined.
10 - pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
11 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
14 - cts-gpios: CTS pin for UART
18 compatible = "microchip,pic32mzda-uart";
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| /Documentation/devicetree/bindings/input/ |
| D | msm-vibrator.txt | 5 - compatible: Should be one of
6 "qcom,msm8226-vibrator"
7 "qcom,msm8974-vibrator"
8 - reg: the base address and length of the IO memory for the registers.
9 - pinctrl-names: set to default.
10 - pinctrl-0: phandles pointing to pin configuration nodes. See
11 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
12 - clock-names: set to pwm
13 - clocks: phandle of the clock. See
14 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /Documentation/devicetree/bindings/display/atmel/ |
| D | hlcdc-dc.txt | 1 Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
4 See ../../mfd/atmel-hlcdc.txt for more details.
7 - compatible: value should be "atmel,hlcdc-display-controller"
8 - pinctrl-names: the pin control state names. Should contain "default".
9 - pinctrl-0: should contain the default pinctrl states.
10 - #address-cells: should be set to 1.
11 - #size-cells: should be set to 0.
20 according to ../../media/video-interfaces.txt, specifically
21 - bus-width: recognized values are <12>, <16>, <18> and <24>, and
28 compatible = "atmel,sama5d3-hlcdc";
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,enc28j60.txt | 9 - compatible: Should be "microchip,enc28j60"
10 - reg: Specify the SPI chip select the ENC28J60 is wired to
11 - interrupts: Specify the interrupt index within the interrupt controller (referred
12 to above in interrupt-parent) and interrupt type. The ENC28J60 natively
15 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
16 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
17 see also generic and your platform specific pinctrl binding
21 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
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| /Documentation/devicetree/bindings/net/can/ |
| D | m_can.txt | 2 -------------------------------------------------
5 - compatible : Should be "bosch,m_can" for M_CAN controllers
6 - reg : physical base address and size of the M_CAN
8 - reg-names : Should be "m_can" and "message_ram"
9 - interrupts : Should be the interrupt number of M_CAN interrupt
12 - interrupt-names : Should contain "int0" and "int1"
13 - clocks : Clocks used by controller, should be host clock
15 - clock-names : Should contain "hclk" and "cclk"
16 - pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
17 - pinctrl-names : Names corresponding to the numbered pinctrl states
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| /Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
13 - interrupts: The interrupt signal from the hdmi block.
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-rockchip.txt | 8 - compatible: should be one of the following.
9 "rockchip,rv1108-spi" for rv1108 SoCs.
10 "rockchip,px30-spi", "rockchip,rk3066-spi" for px30 SoCs.
11 "rockchip,rk3036-spi" for rk3036 SoCS.
12 "rockchip,rk3066-spi" for rk3066 SoCs.
13 "rockchip,rk3188-spi" for rk3188 SoCs.
14 "rockchip,rk3228-spi" for rk3228 SoCS.
15 "rockchip,rk3288-spi" for rk3288 SoCs.
16 "rockchip,rk3368-spi" for rk3368 SoCs.
17 "rockchip,rk3399-spi" for rk3399 SoCs.
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