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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-mt65xx.txt3 The Mediatek's Pin controller is used to control SoC pins.
6 - compatible: value should be one of the following.
7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
14 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
15 controller. It controls the input/output settings on the available pins and
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
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/Documentation/devicetree/bindings/gpio/
Dgpio-vf610.txt3 The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
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Dgpio-mxs.txt4 GPIOs are organized in port/bank. Each port consists of 32 GPIOs.
8 will be represented as sub-nodes of MXS pinctrl node.
11 - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
22 1 = low-to-high edge triggered.
23 2 = high-to-low edge triggered.
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/Documentation/devicetree/bindings/media/i2c/
Dadv7604.txt3 The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
12 - compatible: Must contain one of the following
13 - "adi,adv7611" for the ADV7611
14 - "adi,adv7612" for the ADV7612
16 - reg: I2C slave addresses
17 The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
19 slave device on the I2C bus. The main address is mandatory, others are
22 - hpd-gpios: References to the GPIOs that control the HDMI hot-plug
23 detection pins, one per HDMI input. The active flag indicates the GPIO
24 level that enables hot-plug detection.
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/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-adc.txt3 STM32 ADC is a successive approximation analog-to-digital converter.
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
27 "st,stm32mp1-adc-core"
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/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
30 Cross instances are not allowed. The MU instance can only
54 numbered in "aliases" node.
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/Documentation/driver-api/gpio/
Dlegacy.rst13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
14 digital signal. They are provided from many kinds of chip, and are familiar
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
25 often have a few such pins to help with pin scarcity on SOCs; and there are
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
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/Documentation/networking/
Darcnet-hardware.txt2 -----------------------------------------------------------------------------
5 -----------------------------------------------------------------------------
6 2) This file is no longer Linux-specific. It should probably be moved out of
8 -----------------------------------------------------------------------------
13 e-mail apenwarr@worldvisions.ca with any settings for your particular card,
18 ----------------------
25 there are others as well, but these are less common. The different hardware
26 types, as far as I'm aware, are not compatible and so you cannot wire a
35 There are two "types" of ARCnet - STAR topology and BUS topology. This
36 refers to how the cards are meant to be wired together. According to most
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