Searched +full:pll +full:- +full:periph (Results 1 – 2 of 2) sorted by relevance
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt8 - compatible : shall be one of the following:9 "altr,socfpga-pll-clock" - for a PLL clock10 "altr,socfpga-perip-clock" - The peripheral clock divided from the11 PLL clock.12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.16 - clocks : shall be the input parent clock phandle for the clock. This is17 either an oscillator or a pll output.18 - #clock-cells : from common clock binding, shall be set to 0.[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <maxime.ripard@bootlin.com>14 "#clock-cells":17 "#reset-cells":22 - allwinner,sun4i-a10-ccu23 - allwinner,sun5i-a10s-ccu[all …]