| /Documentation/devicetree/bindings/regulator/ |
| D | max8997-regulator.txt | 7 describes the bindings for 'pmic' sub-block of max8997.
10 - compatible: Should be "maxim,max8997-pmic".
11 - reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
13 - max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
17 - max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
21 - max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
25 [1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
26 property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
30 If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
32 'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
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| D | samsung,s5m8767.txt | 16 - s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
20 - s5m8767,pmic-buck3-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
24 - s5m8767,pmic-buck4-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
28 - s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used
31 [1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
32 property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage'
36 If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
38 's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified.
41 - s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
42 - s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs.
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| D | palmas-pmic.txt | 12 ti,twl6035-pmic
13 ti,twl6036-pmic
14 ti,twl6037-pmic
15 ti,tps65913-pmic
16 ti,tps65914-pmic
17 ti,tps65917-pmic
18 ti,tps659038-pmic
20 ti,palmas-pmic
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
48 ti,mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - auto,
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| D | hisilicon,hi655x-regulator.txt | 4 The Hi655x regulator control is managed by Hi655x PMIC.
6 PMIC node.
17 pmic: pmic@f8000000 {
18 compatible = "hisilicon,hi655x-pmic";
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| D | qcom,rpmh-regulator.txt | 3 rpmh-regulator devices support PMIC regulator management via the Voltage
10 enable state of any PMIC peripheral. It is used for clock buffers, low-voltage
18 level describes the PMIC containing the regulators and must reside within an
19 RPMh device node. The second level describes each regulator within the PMIC
23 The names used for regulator nodes must match those supported by a given PMIC.
33 First Level Nodes - PMIC
47 - qcom,pmic-id
51 this PMIC. Typical values: "a", "b", "c", "d", "e", "f".
60 regulators for this PMIC.
88 regulators for this PMIC.
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| /Documentation/devicetree/bindings/mfd/ |
| D | hisilicon,hi655x.txt | 1 Hisilicon Hi655x Power Management Integrated Circuit (PMIC)
3 The hardware layout for access PMIC Hi655x from AP SoC Hi6220.
4 Between PMIC Hi655x and Hi6220, the physical signal channel is SSI.
15 - compatible: Should be "hisilicon,hi655x-pmic".
16 - reg: Base address of PMIC on Hi6220 SoC.
18 - pmic-gpios: The GPIO used by PMIC IRQ.
26 pmic: pmic@f8000000 {
27 compatible = "hisilicon,hi655x-pmic";
31 pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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| D | max8998.txt | 8 PMIC sub-block
11 The PMIC sub-block contains a number of voltage and current regulators,
20 - reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
26 - max8998,pmic-buck1-dvs-gpios: GPIO specifiers for two host gpios used
29 - max8998,pmic-buck2-dvs-gpio: GPIO specifier for host gpio used
32 - max8998,pmic-buck1-default-dvs-idx: Default voltage setting selected from
36 - max8998,pmic-buck2-default-dvs-idx: Default voltage setting selected from
40 - max8998,pmic-buck-voltage-lock: If present, disallows changing of
43 Additional properties required if max8998,pmic-buck1-dvs-gpios is defined:
44 - max8998,pmic-buck1-dvs-voltage: An array of 4 voltage values in microvolts
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| D | samsung,sec-core.txt | 24 - "samsung,s2mpa01-pmic",
25 - "samsung,s2mps11-pmic",
26 - "samsung,s2mps13-pmic",
27 - "samsung,s2mps14-pmic",
28 - "samsung,s2mps15-pmic",
29 - "samsung,s2mpu02-pmic",
30 - "samsung,s5m8767-pmic".
31 - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
35 - samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled
38 - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
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| D | max77686.txt | 3 MAX77686 is a Multifunction device with PMIC, RTC and Charger on chip. It is
4 interfaced to host controller using i2c interface. PMIC and Charger submodules
8 PMIC submodule.
16 - reg : Specifies the i2c slave address of PMIC block.
21 max77686: pmic@9 {
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| D | da9055.txt | 1 * Dialog DA9055 Power Management Integrated Circuit (PMIC)
15 is instantiated separately from the PMIC.
23 - compatible : Should be "dlg,da9055-pmic"
48 pmic: da9055-pmic@5a {
49 compatible = "dlg,da9055-pmic";
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| D | qcom,spmi-pmic.txt | 35 or generalized "qcom,spmi-pmic".
46 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
49 Each child node of SPMI slave id represents a function of the PMIC. In the
56 compatible = "qcom,spmi-pmic-arb";
59 compatible = "qcom,pm8941", "qcom,spmi-pmic";
70 compatible = "qcom,pm8941", "qcom,spmi-pmic";
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| D | sprd,sc27xx-pmic.txt | 1 Spreadtrum SC27xx Power Management Integrated Circuit (PMIC)
4 and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all
26 - #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2.
31 pmic@0 {
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| D | max77802.txt | 3 The Maxim MAX77802 is a Power Management IC (PMIC) that contains 10 high
15 - reg : Specifies the I2C slave address of PMIC block.
20 max77802: pmic@9 {
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| D | rohm,bd71837-pmic.txt | 20 - clocks : The parent clock connected to PMIC. If this is missing
31 are called as SNVS and READY. At READY state all the PMIC power outputs go
35 reset is done via SNVS state the PMIC OTP data is not reload. This causes
61 pmic: pmic@4b {
89 clocks = <&pmic>;
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| /Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 1 Qualcomm SPMI Controller (PMIC Arbiter)
3 The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
17 - compatible : should be "qcom,spmi-pmic-arb".
22 Registers used only for V2 PMIC Arbiter:
26 - reg : address + size pairs describing the PMIC arb register sets; order must
31 - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
32 - interrupts : interrupt list for the PMIC Arb controller, must contain a
36 "periph_irq" - summary interrupt for PMIC peripherals
37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | pwrap.txt | 1 MediaTek PMIC Wrapper Driver
3 This document describes the binding for the MediaTek PMIC wrapper.
5 On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
6 is not directly visible to the CPU, but only through the PMIC wrapper
7 inside the SoC. The communication between the SoC and the PMIC can
13 on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
44 - pmic: Using either MediaTek PMIC MFD as the child device of pwrap
64 pmic {
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-mt6323.txt | 1 Device Tree Bindings for LED support on MT6323 PMIC
3 MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
5 PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
6 using shared bus called PMIC wrapper for each subfunction to access remote
7 MT6323 PMIC hardware.
11 For MediaTek PMIC wrapper bindings see:
33 mt6323: pmic {
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| /Documentation/devicetree/bindings/power/reset/ |
| D | mt6323-poweroff.txt | 1 Device Tree Bindings for Power Controller on MediaTek PMIC
3 The power controller which could be found on PMIC is responsible for externally
8 "mediatek,mt6323-pwrc": for MT6323 PMIC
12 pmic {
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| /Documentation/devicetree/bindings/sound/ |
| D | mt6351.txt | 3 The communication between MT6351 and SoC is through Mediatek PMIC wrapper.
4 For more detail, please visit Mediatek PMIC wrapper documentation.
6 Must be a child node of PMIC wrapper.
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| D | mt6358.txt | 3 The communication between MT6358 and SoC is through Mediatek PMIC wrapper.
4 For more detail, please visit Mediatek PMIC wrapper documentation.
6 Must be a child node of PMIC wrapper.
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mt65xx.txt | 24 one bus has more than two i2c controllers, if enable have-pmic need include
25 "pmic" extra.
30 - mediatek,have-pmic: platform can control i2c form special pmic side.
42 mediatek,have-pmic;
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-spmi-temp-alarm.txt | 1 Qualcomm QPNP PMIC Temperature Alarm
3 QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
5 interrupt signal and status register to identify high PMIC die temperature.
10 - interrupts: PMIC temperature alarm interrupt.
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| /Documentation/devicetree/bindings/input/ |
| D | mtk-pmic-keys.txt | 1 MediaTek MT6397/MT6323 PMIC Keys Device Driver
3 There are two key functions provided by MT6397/MT6323 PMIC, pwrkey
5 node provided by MT6397/MT6323 PMIC that is being defined as one kind
23 pmic: mt6397 {
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| D | st,stpmic1-onkey.txt | 8 onkey-falling: happens when onkey is pressed; IT_PONKEY_F of pmic
9 onkey-rising: happens when onkey is released; IT_PONKEY_R of pmic
24 interrupt-parent = <&pmic>;
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| /Documentation/devicetree/bindings/clock/ |
| D | cirrus,lochnagar.txt | 46 - ln-pmic-32k : On board fixed clock.
63 - ln-pmic-32k : 32768 Hz
81 clock-names = "ln-gf-mclk2", "ln-pmic-32k";
86 <&clk-pmic>;
89 clk-pmic: clk-pmic {
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