| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
24 - arm,cortex-a73-pmu
25 - arm,cortex-a72-pmu
26 - arm,cortex-a57-pmu
27 - arm,cortex-a53-pmu
28 - arm,cortex-a35-pmu
29 - arm,cortex-a17-pmu
[all …]
|
| D | arm-dsu-pmu.txt | 1 * ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
5 form a multicore cluster. The PMU enables to gather various statistics on
6 the operations of the DSU. The PMU provides independent 32bit counters that
8 The PMU is accessed via CPU system registers and has no MMIO component.
10 ** DSU PMU required properties:
14 "arm,dsu-pmu"
23 dsu-pmu-0 {
24 compatible = "arm,dsu-pmu";
|
| D | cci.txt | 83 - CCI PMU node
87 A CCI pmu node must contain the following properties:
93 "arm,cci-400-pmu,r0"
94 "arm,cci-400-pmu,r1"
95 "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
97 "arm,cci-500-pmu,r0"
98 "arm,cci-550-pmu,r0"
120 The CCI PMU has an interrupt signal for each
209 pmu@9000 {
210 compatible = "arm,cci-400-pmu";
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,dove-pinctrl.txt | 9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
[all …]
|
| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
4 The following PMU devices are supported:
11 The following section describes the SoC PMU DT node binding.
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
19 - reg : First resource shall be the CPU bus PMU resource.
20 - interrupts : Interrupt-specifier for PMU IRQ.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
[all …]
|
| D | nds32v3-pmu.txt | 3 NDS32 core have a PMU for counting cpu and cache events like cache misses.
4 The NDS32 PMU representation in the device tree should be done as under:
9 "andestech,nds32v3-pmu"
11 - interrupts : The interrupt number for NDS32 PMU is 13.
14 pmu{
15 compatible = "andestech,nds32v3-pmu";
|
| D | fsl-imx-ddr.txt | 6 "fsl,imx8-ddr-pmu"
7 "fsl,imx8m-ddr-pmu"
16 ddr-pmu@5c020000 {
17 compatible = "fsl,imx8-ddr-pmu";
|
| /Documentation/devicetree/bindings/arm/samsung/ |
| D | pmu.txt | 1 SAMSUNG Exynos SoC series PMU Registers
5 - "samsung,exynos3250-pmu" - for Exynos3250 SoC,
6 - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
7 - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
8 - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
9 - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
10 - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
11 - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
12 - "samsung,exynos5433-pmu" - for Exynos5433 SoC.
13 - "samsung,exynos7-pmu" - for Exynos7 SoC.
[all …]
|
| /Documentation/devicetree/bindings/soc/dove/ |
| D | pmu.txt | 1 Device Tree bindings for Marvell PMU
4 - compatible: value should be "marvell,dove-pmu".
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
27 - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
28 - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
29 - resets: points to the reset manager (PMU node) and reset index.
33 pmu: power-management@d0000 {
34 compatible = "marvell,dove-pmu";
[all …]
|
| /Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 2 APM X-Gene SoC Performance Monitoring Unit (PMU)
5 X-Gene SoC PMU consists of various independent system device PMUs such as
7 controller(s). These PMU devices are loosely architected to follow the
8 same model as the PMU for ARM cores. The PMUs share the same top level
11 PMU (perf) driver
14 The xgene-pmu driver registers several perf PMU drivers. Each of the perf
24 Most of the SoC PMU has a specific list of agent ID used for monitoring
26 a specific CPU or an I/O bridge. Each PMU has a set of 2 registers capable of
32 each PMU, please refer to APM X-Gene User Manual.
35 single CPU ID of the processor which will be used to handle all the PMU events.
[all …]
|
| D | hisi-pmu.rst | 2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
15 HiSilicon SoC uncore PMU driver
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
39 ID used to count the uncore PMU event.
44 hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
46 hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
48 hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
50 hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
[all …]
|
| D | index.rst | 10 hisi-pmu
14 xgene-pmu
16 thunderx2-pmu
|
| D | arm-ccn.rst | 10 PMU (perf) driver
13 The CCN driver registers a perf PMU driver, which provides
26 Crosspoint PMU events require "xp" (index), "bus" (bus number)
44 the CCN PMU events. It is recommended that the user space tools
52 ccn/cycles/ [Kernel PMU event]
54 ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event]
|
| D | arm_dsu_pmu.rst | 2 ARM DynamIQ Shared Unit (DSU) PMU
6 control logic and external interfaces to form a multicore cluster. The PMU
10 The PMU can only be accessed via CPU system registers and are common to the
12 PMU doesn't support process specific events and cannot be used in sampling mode.
|
| /Documentation/devicetree/bindings/csky/ |
| D | pmu.txt | 9 PMU node bindings definition
12 Description: Describes PMU
19 Definition: must be "csky,csky-pmu"
23 Definition: must be pmu irq num defined by soc
27 Definition: the width of pmu counter
33 pmu: performace-monitor {
34 compatible = "csky,csky-pmu";
|
| /Documentation/devicetree/bindings/sram/ |
| D | rockchip-pmu-sram.txt | 1 Rockchip SRAM for pmu:
4 The sram of pmu is used to store the function of resume from maskrom(the 1st
5 level loader). This is a common use of the "pmu-sram" because it keeps power
9 - compatible : should be "rockchip,rk3288-pmu-sram"
14 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
|
| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | pmu.txt | 4 The pmu is used to turn off and on different power domains of the SoCs
9 "amlogic,meson8-pmu"
10 "amlogic,meson8b-pmu"
15 pmu@c81000e4 {
16 compatible = "amlogic,meson8b-pmu", "syscon";
|
| /Documentation/powerpc/ |
| D | pmu-ebb.rst | 2 PMU Event Based Branches
12 One type of event for which EBBs can be configured is PMU exceptions. This
13 document describes the API for configuring the Power PMU to generate EBBs,
22 attr.config. All events which can be configured on the hardware PMU are
29 When a PMU EBB occurs it is delivered to the currently running process. As such
43 When the PMU is configured for EBBs, all PMU interrupts are delivered to the
44 user process. This means once an EBB event is scheduled on the PMU, no non-EBB
95 guarantee that it has been scheduled on the PMU. To ensure that the EBB event
96 has been scheduled on the PMU, you must perform a read() on the event. If the
101 EBB event is enabled it will force all other non-pinned events off the PMU. In
[all …]
|
| /Documentation/devicetree/bindings/arm/rockchip/ |
| D | pmu.txt | 4 The pmu is used to turn off and on different power domains of the SoCs
8 - compatible value : = "rockchip,rk3066-pmu";
13 pmu@20004000 {
14 compatible = "rockchip,rk3066-pmu";
|
| /Documentation/devicetree/bindings/power/ |
| D | rockchip-io-domain.txt | 35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
41 - "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
43 - "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains
45 - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains
65 Possible supplies for PX30 pmu-domains:
107 Possible supplies for rk3368 pmu-domains:
108 - pmu-supply: The supply connected to PMUIO_VDD.
117 Possible supplies for rk3399 pmu-domains:
|
| /Documentation/ABI/testing/ |
| D | sysfs-hypervisor-xen | 12 What: /sys/hypervisor/pmu/pmu_mode
17 Describes mode that Xen's performance-monitoring unit (PMU)
19 "off" -- PMU is disabled
27 What: /sys/hypervisor/pmu/pmu_features
32 Describes Xen PMU features (as an integer). A set bit indicates
|
| D | sysfs-bus-event_source-devices-events | 30 What: /sys/bus/event_source/devices/<pmu>/events/<event>
33 Description: Per-pmu performance monitoring events specific to the running system
37 performance monitoring event supported by the <pmu>. The name
45 /sys/bus/event_source/devices/<pmu>/format/ and <value> is
67 What: /sys/bus/event_source/devices/<pmu>/events/<event>.unit
79 What: /sys/bus/event_source/devices/<pmu>/events/<event>.scale
|
| /Documentation/devicetree/bindings/devfreq/event/ |
| D | rockchip-dfi.txt | 7 - rockchip,pmu: phandle to the syscon managing the "pmu general register files"
15 rockchip,pmu = <&pmugrf>;
|
| /Documentation/devicetree/bindings/phy/ |
| D | samsung-phy.txt | 12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
37 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
38 control pmu registers for power isolation.
54 - samsung,pmureg-phandle - handle to syscon used to control PMU registers
113 - samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
164 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
165 control pmu registers for power isolation.
180 samsung,pmu-syscon = <&pmu_system_controller>;
|
| /Documentation/devicetree/bindings/power/reset/ |
| D | syscon-reboot-mode.txt | 23 pmu: pmu@20004000 {
24 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
|