Searched full:ports (Results 1 – 25 of 331) sorted by relevance
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| /Documentation/leds/ |
| D | ledtrig-usbport.rst | 9 It requires selecting USB ports that should be observed. All available ones are
10 listed as separated entries in a "ports" subdirectory. Selecting is handled by
13 Please note that this trigger allows selecting multiple USB ports for a single
18 1) Device with single USB LED and few physical ports
29 only one LED user will most likely want to assign ports from all 3 hubs.
43 echo 1 > ports/usb1-port1
44 echo 1 > ports/usb2-port1
45 cat ports/usb1-port1
46 echo 0 > ports/usb1-port1
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 4 On CPM1 devices, all ports are using slightly different register layouts.
5 Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
7 On CPM2 devices, all ports are 32bit ports and use a common register layout.
18 on CPM1), this item tells which ports have an associated interrupt (ports are
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| /Documentation/ABI/stable/ |
| D | sysfs-class-infiniband | 37 What: /sys/class/infiniband/<device>/ports/<port-num>/lid
38 What: /sys/class/infiniband/<device>/ports/<port-num>/rate
39 What: /sys/class/infiniband/<device>/ports/<port-num>/lid_mask_count
40 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_sl
41 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_lid
42 What: /sys/class/infiniband/<device>/ports/<port-num>/state
43 What: /sys/class/infiniband/<device>/ports/<port-num>/phys_state
44 What: /sys/class/infiniband/<device>/ports/<port-num>/cap_mask
73 What: /sys/class/infiniband/<device>/ports/<port-num>/link_layer
81 What: /sys/class/infiniband/<device>/ports/<port-num>/counters/symbol_error
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | abilis,tb10x-iomux.txt | 25 - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
27 - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
28 - Parallel TS input ports: mip1, mip3, mip5, mip7
29 - Serial TS output ports: mos0, mos1, mos2, mos3
33 - Smart card ports: stc0, stc1
34 - UART ports: uart0, uart1
35 - SPI ports: spi1, spi3
38 All other ports of the chip are not multiplexed and thus not managed by this
45 The named pin groups of GPIO ports can be used to define GPIO ranges as
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| /Documentation/devicetree/bindings/arm/ |
| D | coresight.txt | 60 * port or ports: see "Graph bindings for Coresight" below.
88 * port or ports: see "Graph bindings for Coresight" below.
118 * All output ports must be listed inside a child node named "out-ports"
119 * All input ports must be listed inside a child node named "in-ports".
131 in-ports {
146 in-ports {
161 in-ports {
169 out-ports {
185 out-ports {
189 /* replicator output ports */
[all …]
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | par_io.txt | 1 * Parallel I/O Ports
3 This node configures Parallel I/O ports for CPUs with QE support.
5 device that using parallel I/O ports, a child node should be created.
12 - num-ports : number of Parallel I/O ports
20 num-ports = <7>;
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| /Documentation/hwmon/ |
| D | it87.rst | 10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
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| /Documentation/networking/dsa/ |
| D | configuration.rst | 91 # The master interface needs to be brought up before the slave ports.
104 # The master interface needs to be brought up before the slave ports.
115 # add ports to bridge
131 # The master interface needs to be brought up before the slave ports.
145 # add ports to bridge
175 # The master interface needs to be brought up before the slave ports.
192 # add ports to bridges
197 # tag traffic on ports
219 # The master interface needs to be brought up before the slave ports.
234 # add ports to bridge
[all …]
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| D | lan9303.rst | 6 the two external ethernet ports. The third port is an RMII/MII interface to a
24 When both user ports are joined to the same bridge, the normal HW MAC learning
29 If one of the user ports leave the bridge, the ports goes back to the initial
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| D | b53.rst | 71 # The master interface needs to be brought up before the slave ports.
88 # add ports to bridges
93 # tag traffic on ports
116 # The master interface needs to be brought up before the slave ports.
131 # add ports to bridge
152 # The master interface needs to be brought up before the slave ports.
168 # add ports to bridges
174 # tag traffic on ports
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| /Documentation/devicetree/bindings/ |
| D | graph.txt | 14 have multiple specifiable ports, each of which can be linked to one or more
15 ports of other devices.
23 Here the ports describe data interfaces, and the links between them are
27 Organisation of ports and endpoints
30 Ports are described by child 'port' nodes contained in the device node.
66 All 'port' nodes can be grouped under an optional 'ports' node, which
73 ports {
95 containing ports.
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| /Documentation/devicetree/bindings/serial/ |
| D | samsung_uart.txt | 9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
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| /Documentation/devicetree/bindings/media/ |
| D | imx.txt | 13 - ports : Should contain a list of phandles pointing to camera
14 sensor interface ports of IPU devices
20 ports = <&ipu1_csi0>, <&ipu1_csi1>;
46 connecting with a MIPI CSI-2 source, and ports 1
47 through 4 are output ports connecting with parallel
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| /Documentation/devicetree/bindings/ata/ |
| D | marvell.txt | 7 - nr-ports : Number of SATA ports in use.
21 nr-ports = <2>;
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| /Documentation/devicetree/bindings/usb/ |
| D | usb3503.txt | 10 - disabled-ports: Should specify the ports unused.
13 Do not describe this property if all ports have to be enabled.
33 disabled-ports = <2 3>;
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| D | usb251xb.txt | 44 - non-removable-ports : Should specify the ports which have a non-removable
46 - sp-disabled-ports : Specifies the ports which will be self-power disabled
47 - bp-disabled-ports : Specifies the ports which will be bus-power disabled
67 - swap-dx-lanes : Specifies the ports which will swap the differential-pair
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
7 input port is a single lane 800Mbps. Both ports support clock and data lane
25 - ports: A ports node with one port child node per device input and output
60 ports {
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,dsi.txt | 22 - ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
23 2 ports are available:
29 Other ports will be added later to support the new kind of inputs.
46 ports {
77 ports {
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| D | tda998x.txt | 21 - video-ports: 24 bits value which defines how the video controller
24 - audio-ports: array of 8-bit values, 2 values per one DAI[1].
47 video-ports = <0x230145>;
51 audio-ports = < TDA998x_SPDIF 0x04
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| /Documentation/devicetree/bindings/display/sunxi/ |
| D | sun4i-drm.txt | 62 - ports: A ports node with endpoint definitions as defined in
101 - ports: A ports node with endpoint definitions as defined in
143 - ports: A ports node with endpoint definitions as defined in
184 - ports: A ports node with endpoint definitions as defined in
253 - ports: A ports node with endpoint definitions as defined in
254 Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
264 (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one
292 - ports: A ports node with endpoint definitions as defined in
320 - ports: A ports node with endpoint definitions as defined in
350 - ports: A ports node with endpoint definitions as defined in
[all …]
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| /Documentation/sound/cards/ |
| D | emu10k1-jack.rst | 32 This will give you 16 input ports and 16 output ports.
34 The 16 output ports map onto the 16 FX buses (or the first 16 of 64, for the
38 The 16 input ports are connected to the 16 physical inputs. Contrary to
48 the second and third input ports are wired to the center/LFE output. You will
52 ports to FXBUS2 (multitrack recording input) and EXTOUT (physical output)
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| /Documentation/ABI/testing/ |
| D | configfs-usb-gadget-midi | 11 in_ports - number of MIDI input ports
12 out_ports - number of MIDI output ports
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 36 The number of ports implemented by each GPIO controller varies. The number of
43 describes the port-level mapping. In that file, the naming convention for ports
49 represents the aggregate status for all GPIOs within a set of ports. Thus, the
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
55 of ports. Each GPIO may be configured to feed into a specific one of the
56 interrupt signals generated by a set-of-ports. The intent is for each generated
91 The interrupt outputs from the HW block, one per set of ports, in the
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| /Documentation/devicetree/bindings/net/ |
| D | hisilicon-hns-nic.txt | 12 are called debug ports.
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
26 In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a
43 In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports
54 ports connected to a LAN Switch while the CPU side assume itself have one
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | dsa.txt | 12 - ports : A container for child nodes representing switch ports.
22 The ports container has the following properties
37 towards the phandle ports. The full routing
86 ports {
138 ports {
205 ports {
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