Searched full:processor (Results 1 – 25 of 359) sorted by relevance
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| /Documentation/ABI/testing/ |
| D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
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| D | sysfs-bus-rpmsg | 7 processor. Channels are identified with a (textual) name,
19 processor. Channels have a local ("source") rpmsg address,
37 processor. Channels have a local ("source") rpmsg address,
48 remote processor. This make it a local rpmsg server,
59 processor. Channels are identified by a textual name (see
69 to the other processor, in order to let it know about the
83 processor. Channels are identified by a textual name (see
89 remote processor is referred as rpmsg driver. The rpmsg device
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.txt | 4 information between the processors in a Qualcomm SoC. Each processor is
5 assigned 32 bits of state that can be modified. A processor can through a
7 certain bit owned by a certain remote processor.
19 signaling the N:th remote processor
27 Definition: identifier of the local processor in the list of hosts, or
29 matrix representing the local processor
43 Each processor's state bits are described by a subnode of the smsm device node.
45 processor's state bits or the local processors bits. The node names are not
63 to belong to a remote processor
73 Definition: one entry specifying remote IRQ used by the remote processor
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| D | qcom,smd.txt | 15 processor of some sort - or in SMD language an "edge". The name of the edges
22 Definition: should specify the IRQ used by the remote processor to
23 signal this processor about communication related updates
35 signaling the remote processor:
43 Definition: the identifier of the remote processor in the smd channel
49 Definition: the identifier for the remote processor as known by the rest
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| /Documentation/admin-guide/acpi/ |
| D | cppc_sysfs.rst | 4 Collaborative Processor Performance Control (CPPC)
11 performance of a logical processor on a contigious and abstract performance
38 * highest_perf : Highest performance of this processor (abstract scale).
39 * nominal_perf : Highest sustained performance of this processor
41 * lowest_nonlinear_perf : Lowest performance of this processor with nonlinear
43 * lowest_perf : Lowest performance of this processor (abstract scale).
47 The above frequencies should only be used to report processor performance in
52 Reference counter ticks up proportional to processor's reference performance.
53 Delivered counter ticks up proportional to processor's delivered performance.
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 25 1) Processor TDP (Thermal design power)
28 processor varies based on the workload being executed. Derated power
36 be calculated using different processor northbridge function
41 consumed by the processor for NB and logic external to the core.
45 the processor can support.
48 consumed by the processor.
57 attributes only for internal node0 of a multi-node processor.
62 calculate the average power consumed by a processor during a
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| D | k10temp.rst | 73 AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
77 AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
81 AMD Family 10h Desktop Processor Power and Thermal Data Sheet:
99 socket type, not the processor's actual capabilities. Therefore, if you
100 are using an AM3 processor on an AM2+ mainboard, you can safely use the
107 Tctl is the processor temperature control value, used by the platform to
111 the processor temperature relative to the point at which the system must
112 supply the maximum cooling for the processor's specified maximum case
118 which the processor will throttle itself to avoid damage is available in
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| D | asc7621.rst | 117 - Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies
137 peci_legacy = 1, PECI Processor Temperature 0
141 4 PECI Processor Temperature 0
142 5 PECI Processor Temperature 1
143 6 PECI Processor Temperature 2
144 7 PECI Processor Temperature 3
153 4 PECI Processor Temperature 0
154 5 PECI Processor Temperature 1
155 6 PECI Processor Temperature 2
156 7 PECI Processor Temperature 3
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| D | scpi-hwmon.rst | 6 * Chips based on ARM System Control Processor Interface
18 System Control Processor (SCP) implementing the System Control
19 Processor Interface (SCPI). The following sensor types are supported
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| /Documentation/ |
| D | this_cpu_ops.txt | 9 variables associated with the *currently* executing processor. This is
12 specific processor).
14 this_cpu operations add a per cpu variable offset to the processor
21 processor is not changed between the calculation of the address and
33 data specific to the currently executing processor. Only the current
34 processor should be accessing that variable and therefore there are no
71 the processor. So the relocation to the per cpu base is encoded in the
88 prevent the kernel from moving the thread to a different processor
111 reserved for a specific processor. Without disabling preemption in the
116 the value of the individual counters for each processor are
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| D | rpmsg.txt | 2 Remote Processor Messaging (rpmsg) Framework
14 Modern SoCs typically employ heterogeneous remote processor devices in
26 multimedia tasks from the main application processor.
34 hardware accessible only by the remote processor, reserving kernel-controlled
35 resources on behalf of the remote processor, etc..).
48 to the processor. To minimize the risks of rogue (or buggy) userland code
54 Every rpmsg device is a communication channel with a remote processor (thus
73 sends a message across to the remote processor on a given channel.
80 one becomes available (i.e. until the remote processor consumes
92 sends a message across to the remote processor on a given channel,
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| D | remoteproc.txt | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
54 Power off a remote processor (previously booted with rproc_boot()).
75 the remote processor's refcount, so always use rproc_put() to
90 /* let's power on and boot our remote processor */
99 * our remote processor is now powered on... give it some work
115 Allocate a new remote processor handle, but don't register
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | st-rproc.txt | 1 STMicroelectronics Co-Processor Bindings
7 the bootloader starts a co-processor, the primary OS must detect its state
17 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
18 - clock-frequency Clock frequency to set co-processor at if the bootloader
21 for the co-processor
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| D | stm32-rproc.txt | 9 remote processor.
10 - resets: Reference to a reset controller asserting the remote processor.
12 remote processor reset hold boot
43 memories shared with the remote processor (eg: remoteproc
47 processor deep sleep setting
52 firmware and starts the remote processor.
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| D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
56 the remote processor to the host processor. The values should
67 stack. This will be used to interrupt the remote processor.
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| D | imx-rproc.txt | 1 NXP iMX6SX/iMX7D Co-Processor Bindings
4 This binding provides support for ARM Cortex M4 Co-processor found on some
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
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| /Documentation/admin-guide/pm/ |
| D | intel_pstate.rst | 60 on the capabilities of the processor.
86 enabled in the processor and possibly on the processor model.
96 If the processor supports the HWP feature, it will be enabled during the
97 processor initialization and cannot be disabled after that. It is possible
101 If the HWP feature has been enabled, ``intel_pstate`` relies on the processor to
102 select P-states by itself, but still it can give hints to the processor's
107 Even though the P-state selection is carried out by the processor automatically,
116 In this configuration ``intel_pstate`` will write 0 to the processor's
118 Energy-Performance Bias (EPB) knob (otherwise), which means that the processor's
124 Also, in this configuration the range of P-states available to the processor's
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| /Documentation/powerpc/ |
| D | vcpudispatch_stats.txt | 4 For Shared Processor LPARs, the POWER Hypervisor maintains a relatively
5 static mapping of the LPAR processors (vcpus) to physical processor
7 on their associated physical processor chip. However, under certain
8 scenarios, vcpus may be dispatched on a different processor chip (away
26 2. number of times this vcpu was dispatched on the same processor as last
28 3. number of times this vcpu was dispatched on a different processor core
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| /Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 6 various processor subsystems and is connected on an interconnect bus. The
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
53 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
77 used for the communication between the host processor and a remote processor.
95 multiple interrupt lines connected to the MPU processor.
105 processor on AM33xx/AM43xx SoCs.
109 A device needing to communicate with a target processor device should specify
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | gamecube.txt | 16 Represents the interface between the graphics processor and a external
25 1.b) The Processor Interface (PI) node
27 Represents the data and control interface between the main processor
28 and graphics and audio processor.
47 Represents the digital signal processor interface, designed to offload
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| D | wii.txt | 25 Represents the interface between the graphics processor and a external
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
37 and graphics and audio processor.
58 Represents the digital signal processor interface, designed to offload
130 1.j) The Inter-Processor Communication (IPC) node
132 Represent the Inter-Processor Communication interface. This interface
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| /Documentation/cpu-freq/ |
| D | pcc-cpufreq.txt | 27 Processor Clocking Control Driver
46 Processor Clocking Control (PCC) is an interface between the platform
47 firmware and OSPM. It is a mechanism for coordinating processor
54 OS wants for a logical processor. The platform firmware attempts to achieve
62 http://www.acpica.org/download/Processor-Clocking-Control-v1p0.pdf
78 The ACPI PCCP() method is implemented for each logical processor and is
82 When PCC mode is enabled, the platform will not expose processor performance
88 computes the required performance for each processor based on server workload.
101 processor since the last time this command was completed. The output buffer
102 indicates the average unhalted frequency of the logical processor expressed as
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 22 fetch and execute instructions: hardware threads, if present, or processor
25 with it, there is an opportunity to save energy for the processor that it
27 instructions from memory and putting some of the processor's functional units
32 (from the kernel perspective) and ask the processor to use (or "enter") that
40 units: *governors* responsible for selecting idle states to ask the processor
50 select an idle state to ask the processor to enter in order to save some energy.
92 processor holding the given CPU can be asked to enter).
119 Called to select an idle state for the processor holding the (logical)
131 the scheduler tick before asking the processor to enter the selected
134 processor will be asked to enter the selected idle state without
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | qcom,cmd-db.txt | 5 resource address for a system resource managed by a remote processor. The data
6 is stored in a shared memory region and is loaded by the remote processor.
11 remote processor and made available in the shared memory.
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| /Documentation/ABI/stable/ |
| D | sysfs-firmware-opal-elog | 13 Log entries may be purged by the service processor
19 the service processor needs more room for log entries,
26 The service processor may be able to store more log
56 the service processor, if applicable).
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