Searched full:receive (Results 1 – 25 of 318) sorted by relevance
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| /Documentation/infiniband/ |
| D | tag_matching.rst | 14 The ordering rules require that when more than one pair of send and receive
16 and the earliest posted-receive is the pair that must be used to satisfy the
23 corresponding matching receive is posted. If a matching receive is posted,
44 There are two types of matching objects used, the posted receive list and the
45 unexpected message list. The application posts receive buffers through calls
46 to the MPI receive routines in the posted receive list and posts send messages
47 using the MPI send routines. The head of the posted receive list may be
50 When send is initiated and arrives at the receive side, if there is no
51 pre-posted receive for this arriving message, it is passed to the software and
54 specified receive buffer. This allows overlapping receive-side MPI tag
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| /Documentation/networking/ |
| D | scaling.rst | 17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
24 RSS: Receive Side Scaling
27 Contemporary NICs support multiple receive and transmit descriptor queues
31 of logical flows. Packets for each flow are steered to a separate receive
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
42 stores a queue number. The receive queue for a packet is determined
49 can be directed to their own receive queue. Such “n-tuple” filters can
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| D | strparser.txt | 13 The strparser works in one of two modes: receive callback or general
16 In receive callback mode, the strparser is called from the data_ready
29 functions, and a data_ready function for receive callback mode. The
42 socket associated with the stream parser for use with receive
83 maximum messages size is the limit of the receive socket
84 buffer and message timeout is the receive timeout for the socket.
120 zero) and the parser is in receive callback mode, then it will set
130 processing a timeout). In receive callback mode the default
137 by the lock callback. In receive callback mode the default
158 the TCP socket in receive callback mode. The stream parser may
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| D | altera_tse.txt | 36 The SGDMA supports only a single transmit or receive operation at a time, and
73 4.2) Receive process
74 The driver will post receive buffers to the receive DMA logic during driver
75 initialization. Receive buffers may or may not be queued depending upon the
76 underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
77 to queue receive buffers to the SGDMA receive logic). When a packet is
78 received, the DMA logic generates an interrupt. The driver handles a receive
79 interrupt by obtaining the DMA receive logic status, reaping receive
80 completions until no more receive completions are available.
84 using NAPI for receive operations. Interrupt mitigation is not yet supported
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| D | hinic.txt | 18 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
19 LRO(Large Receive Offload).
76 accumulated on the CEQ that is configured to receive the CMDQ completion events.
79 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
105 Rx Queues - Logical Rx Queues that use the HW Receive Queues for receive.
106 The Logical Rx queue is not dependent on the format of the HW Receive Queue.
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| D | kcm.txt | 6 can efficiently send and receive application protocol messages over TCP using
44 Similarly, in the receive path, messages are constructed on each TCP socket
52 messages on receive as well as other connection specific information for KCM.
60 can be used to send and receive messages from the KCM socket.
95 KCM limits the maximum receive message size to be the size of the receive
102 A timeout may be set for assembling messages on a receive socket. The timeout
103 value is taken from the receive timeout of the attached TCP socket (this is set
185 Disabling receive on KCM socket
189 When receive is disabled, any pending messages in the socket's
190 receive buffer are moved to other sockets. This feature is useful
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-msgr.txt | 25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
53 mpic-msgr-receive-mask = <0x5>;
59 // Message registers 0 and 2 in this block can receive interrupts on
62 mpic-msgr-receive-mask = <0x5>;
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| /Documentation/networking/device_drivers/microsoft/ |
| D | netvsc.txt | 20 Receive Side Scaling
22 Hyper-V supports receive side scaling. For TCP & UDP, packets can
42 Generic Receive Offload, aka GRO
48 Large Receive Offload (LRO), or Receive Side Coalescing (RSC)
73 Receive Buffer
75 Packets are received into a receive area which is created when device
76 is probed. The receive area is broken into MTU sized chunks and each may
77 contain one or more packets. The number of receive sections may be changed
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| /Documentation/networking/device_drivers/neterion/ |
| D | vxge.txt | 45 Checksum offload (TCP/UDP/IP) on transmit and receive paths
47 Generic Receive Offload (GRO) on receive path
56 viii)RTH (Receive Traffic Hash): (Enabled by default)
57 Receive side steering for better scaling.
64 Up to 17 hardware based transmit and receive data channels, with
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| D | s2io.txt | 44 and receive, TSO.
46 c. Multi-buffer receive mode. Scattering of packet across multiple
58 f. Multi-FIFO/Ring. Supports up to 8 transmit queues and receive rings,
68 Number of receive rings
78 Size of each receive ring(in 4K blocks)
120 Receive performance:
127 c. Ensure Receive Checksum offload is enabled. Use "ethtool -K ethX" command to
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,axi-i2s.txt | 3 The core can be generated with transmit (playback), only receive
15 the core. The core expects two dma channels if both transmit and receive are
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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| D | designware-i2s.txt | 12 one for receive.
13 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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| D | fsl-sai.txt | 41 receiver will send and receive data by following
47 receive data by following their own bit clocks and
63 transmitter and receiver will send and receive data by following clocks
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cirrus,clps711x-intc.txt | 25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
32 29: URXINT2 UART2 receive FIFO half full
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-queues | 7 Receive Packet Steering packet processing flow for this
16 Number of Receive Packet Steering flows being currently
17 processed by this particular network device receive queue.
50 Mask of the receive queue(s) currently enabled to participate
53 number of available receive queue(s) in the network device.
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| /Documentation/media/uapi/rc/ |
| D | lirc-get-rec-mode.rst | 20 LIRC_GET_REC_MODE/LIRC_SET_REC_MODE - Get/set current receive mode.
38 Mode used for receive.
43 Get and set the current receive mode. Only
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| D | lirc-set-rec-carrier.rst | 19 LIRC_SET_REC_CARRIER - Set carrier used to modulate IR receive.
40 Set receive carrier used to modulate IR PWM pulses and spaces.
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| /Documentation/networking/device_drivers/intel/ |
| D | ixgb.rst | 95 receive.
119 This value is the number of receive descriptors allocated by the driver.
121 Each descriptor is 16 bytes. A receive buffer is also allocated for
124 receive buffer size is 2048 bytes. When the MTU is greater than 1500 the
125 receive buffer size will be either 4056, 8192, or 16384 bytes. The
142 This value delays the generation of receive interrupts in units of
143 0.8192 microseconds. Receive interrupt reduction can improve CPU
148 run out of available receive descriptors.
175 Receive Flow control high threshold (when we send a pause frame)
182 Receive Flow control low threshold (when we send a resume frame)
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| D | fm10k.rst | 84 NOTE: This driver will attempt to use multiple page sized buffers to receive
86 allocating receive packets.
89 Generic Receive Offload, aka GRO
103 Retrieves the receive network flow classification configurations.
109 Configures the receive network flow classification.
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| /Documentation/devicetree/bindings/spi/ |
| D | microchip,spi-pic32.txt | 7 of <fault-irq>, <receive-irq>, <transmit-irq>.
18 named "spi-tx" for transmit and named "spi-rx" for receive.
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| /Documentation/devicetree/bindings/ata/ |
| D | imx-sata.txt | 21 - fsl,receive-eq-mdB : receive equalisation, in milli-decibels
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| /Documentation/devicetree/bindings/serial/ |
| D | qcom,msm-uartdm.txt | 4 transmit and/or receive channels can be offloaded to a dma-engine. From a
27 - dmas: Should contain dma specifiers for transmit and receive channels
28 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
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| /Documentation/core-api/ |
| D | librs.rst | 111 /* Receive data */
113 /* Receive parity */
128 /* Receive data */
130 /* Receive parity */
150 /* Receive data */
152 /* Receive parity */
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 45 - marvell,rx-queue-size: size of the receive ring buffer.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
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| D | davinci_emac.txt | 15 4 sources: <Receive Threshold Interrupt
16 Receive Interrupt
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