Searched +full:reg +full:- +full:io +full:- +full:width (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | smsc911x.txt | 1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
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| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
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| D | smsc-lan91c111.txt | 4 - compatible = "smsc,lan91c111";
5 - reg : physical address and size of registers
6 - interrupts : interrupt connection
9 - phy-device : see ethernet.txt file in the same directory
10 - reg-io-width : Mask of sizes (in bytes) of the IO accesses that
13 16-bit access only.
14 - power-gpios: GPIO to control the PWRDWN pin
15 - reset-gpios: GPIO to control the RESET pin
16 - pxa-u16-align4 : Boolean, put in place the workaround the force all
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| /Documentation/devicetree/bindings/serial/ |
| D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.txt | 4 - compatible : Should contain "samsung,exynos4210-srom".
6 - reg: offset and length of the register set
12 - #address-cells: Must be set to 2 to allow device address translation.
15 - #size-cells: Must be set to 1 to allow device size passing
17 - ranges: Must be set up to reflect the memory layout with four integer values
19 <bank-number> 0 <parent address of bank> <size>
21 Sub-nodes:
27 - reg: bank number, base address (relative to start of the bank) and size of
31 - samsung,srom-timing : array of 6 integers, specifying bank timings in the
35 Tacp : Page mode access cycle at Page mode (0 - 15)
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_hdmi-rockchip.txt | 9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
20 - reg-io-width: See dw_hdmi.txt. Shall be 4.
21 - interrupts: HDMI interrupt number
22 - clocks: See dw_hdmi.txt.
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon.txt | 5 represent as any specific type of device. The typical use-case is for
6 some other node's driver, or platform-specific code, to acquire a
13 - compatible: Should contain "syscon".
14 - reg: the register region can be accessed from syscon
17 - reg-io-width: the size (in bytes) of the IO accesses that should be
19 - hwlocks: reference to a phandle of a hardware spinlock provider node.
22 gpr: iomuxc-gpr@20e0000 {
23 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
24 reg = <0x020e0000 0x38>;
30 reg = <0x40500000 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | dw_hdmi.txt | 6 specification by itself but is meant to be referenced by platform-specific
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
15 - reg-io-width: Width of the registers specified by the reg property. The
17 register width defaults to 1 if the property is not present.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
21 - clocks: References to all the clocks specified in the clock-names property
22 as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
26 - "iahb" is the bus clock for either AHB and APB (mandatory).
27 - "isfr" is the internal register configuration clock (mandatory).
[all …]
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-pxa.txt | 1 * Marvell sdhci-pxa v2/v3 controller
4 and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
7 - compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
8 "marvell,armada-380-sdhci".
9 - reg:
10 * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
13 * for "marvell,armada-380-sdhci", three register areas. The first
17 - reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
18 for "marvell,armada-380-sdhci"
19 - clocks: Array of clocks required for SDHCI; requires at least one for
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | renesas,r9a06g032-sysctrl.txt | 5 - compatible: Must be:
6 - "renesas,r9a06g032-sysctrl"
7 - reg: Base address and length of the SYSCTRL IO block.
8 - #clock-cells: Must be 1
9 - clocks: References to the parent clocks:
10 - external 40mhz crystal.
11 - external (optional) 32.768khz
12 - external (optional) jtag input
13 - external (optional) RGMII_REFCLK
14 - clock-names: Must be:
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| D | rockchip,rk3036-cru.txt | 9 - compatible: should be "rockchip,rk3036-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "rmii_clkin" - external EMAC clock - optional
[all …]
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| D | rockchip,rv1108-cru.txt | 9 - compatible: should be "rockchip,rv1108-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_vip" - external VIP clock - optional
33 - "ext_i2s" - external I2S clock - optional
[all …]
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| D | rockchip,rk3328-cru.txt | 9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "clkin_i2s" - external I2S clock - optional,
33 - "gmac_clkin" - external GMAC clock - optional
[all …]
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| D | rockchip,rk3228-cru.txt | 9 - compatible: should be "rockchip,rk3228-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
[all …]
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| D | rockchip,rk3368-cru.txt | 9 - compatible: should be "rockchip,rk3368-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
28 The device tree may optionally contain sub-nodes describing partitions of the
33 gpio-nand@1,0 {
34 compatible = "gpio-control-nand";
[all …]
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| D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
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| /Documentation/devicetree/bindings/watchdog/ |
| D | ts4800-wdt.txt | 4 - compatible: must be "technologic,ts4800-wdt"
5 - syscon: phandle / integer array that points to the syscon node which
7 - phandle to FPGA's syscon
8 - offset to the watchdog register
11 - timeout-sec: contains the watchdog timeout in seconds.
16 compatible = "syscon", "simple-mfd";
17 reg = <0xb0010000 0x3d>;
18 reg-io-width = <2>;
21 compatible = "technologic,ts4800-wdt";
23 timeout-sec = <10>;
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| /Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.txt | 4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
5 "jaguar2", or "amazon,alpine-dw-apb-ssi"
6 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
8 - interrupts : One interrupt, used by the controller.
9 - #address-cells : <1>, as required by generic SPI binding.
10 - #size-cells : <0>, also as required by generic SPI binding.
11 - clocks : phandles for the clocks, see the description of clock-names below.
13 is optional. If a single clock is specified but no clock-name, it is the
17 - clock-names : Contains the names of the clocks:
20 - cs-gpios : Specifies the gpio pins to be used for chipselects.
[all …]
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| /Documentation/devicetree/bindings/ipmi/ |
| D | npcm7xx-kcs-bmc.txt | 5 used to perform in-band IPMI communication with their host.
8 - compatible : should be one of
9 "nuvoton,npcm750-kcs-bmc"
10 - interrupts : interrupt generated by the controller
11 - kcs_chan : The KCS channel number in the controller
16 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
17 reg = <0xf0007000 0x40>;
18 reg-io-width = <1>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
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| /Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 4 - compatible
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
15 - clocks: clock number used to generate the pixel clock
17 - resets: reset line that must be released to use the GFX device
19 - memory-region:
21 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
27 compatible = "aspeed,ast2500-gfx", "syscon";
[all …]
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| /Documentation/devicetree/bindings/net/can/ |
| D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
31 - nxp,tx-output-config : TX output pin configuration:
33 <0x02> : TX0 pull-down (default)
34 <0x04> : TX0 pull-up
[all …]
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
9 PARALLEL output port has a maximum width of 12 bits.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | oxnas,pinctrl.txt | 3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
13 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
15 Required properties for pin configuration sub-nodes:
16 - pins: List of pins to which the configuration applies.
18 Optional properties for pin configuration sub-nodes:
19 ----------------------------------------------------
20 - function: Mux function for the specified pins.
21 - bias-pull-up: Enable weak pull-up.
[all …]
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