Searched full:reg (Results 1 – 25 of 2876) sorted by relevance
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6358.txt | 13 - reg : BCM6358 LED controller address and size.
24 - reg : LED pin number (only LEDs 0 to 31 are valid).
41 reg = <0xfffe00d0 0x8>;
44 reg = <0>;
49 reg = <2>;
54 reg = <3>;
59 reg = <4>;
70 reg = <0x100000d0 0x8>;
75 reg = <0>;
80 reg = <1>;
[all …]
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| D | leds-bcm6328.txt | 27 - reg : BCM6328 LED controller address and size.
44 - reg : LED pin number (only LEDs 0 to 23 are valid).
78 reg = <0x10000800 0x24>;
81 reg = <2>;
86 reg = <3>;
91 reg = <4>;
97 reg = <17>;
101 reg = <18>;
105 reg = <19>;
109 reg = <20>;
[all …]
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| D | leds-pca955x.txt | 15 - reg: I2C slave address. depends on the model.
23 - reg : number of LED line.
44 reg = <0x60>;
51 reg = <12>;
55 reg = <13>;
59 reg = <14>;
63 reg = <15>;
70 reg = <0>;
75 reg = <1>;
80 reg = <2>;
[all …]
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| /Documentation/devicetree/bindings/mux/ |
| D | reg-mux.txt | 8 "reg-mux" : if parent device of mux controller is not syscon device
11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
21 pair in the mux-reg-masks array.
30 reg = <0x66>;
33 compatible = "reg-mux";
35 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
36 <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
49 reg = <0x0>;
55 reg = <0x8>;
72 reg = <0x0>;
[all …]
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | qca8k.txt | 49 reg = <0>;
53 reg = <1>;
57 reg = <2>;
61 reg = <3>;
65 reg = <4>;
74 reg = <0x10>;
80 reg = <0>;
91 reg = <1>;
97 reg = <2>;
103 reg = <3>;
[all …]
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| D | dsa.txt | 30 - reg : Describes the port address in the switch
82 reg = <0>;
90 reg = <0>;
95 reg = <1>;
101 reg = <2>;
106 reg = <5>;
117 reg = <6>;
134 reg = <0>;
142 reg = <0>;
148 reg = <1>;
[all …]
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| D | lantiq-gswip.txt | 8 - reg : memory range of the GSWIP core registers
35 - reg : Offset of the GPHY firmware register in the RCU
48 reg = < 0xe108000 0x3100 /* switch */
59 reg = <0>;
66 reg = <1>;
73 reg = <2>;
80 reg = <4>;
87 reg = <5>;
94 reg = <0x6>;
104 reg = <0>;
[all …]
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| D | ksz.txt | 47 reg = <0>;
57 reg = <0>;
61 reg = <1>;
65 reg = <2>;
69 reg = <3>;
73 reg = <4>;
77 reg = <5>;
89 reg = <0>;
99 reg = <0>;
103 reg = <1>;
[all …]
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| D | mt7530.txt | 33 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
85 reg = <0>;
94 reg = <0>;
96 reg = <0>;
101 reg = <1>;
106 reg = <2>;
111 reg = <3>;
116 reg = <4>;
121 reg = <6>;
139 reg = <0>;
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 17 - reg : shall be the physical PLL register address for the pll clock.
27 - reg : shall be the physical register address for the pmd clock.
36 - reg : shall be a list of address and length pairs describing the CSR
39 - reg-names : shall be a string list describing the reg resource. This
40 may include "csr-reg" and/or "div-reg". If this property
41 is not present, the reg property is assumed to describe
42 only "csr-reg".
67 reg = <0x0 0x17000100 0x0 0x1000>;
76 reg = <0x0 0x7e200200 0x0 0x10>;
85 reg = <0x0 0x17000120 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 6 - reg: Physical base address of the IP registers and length of memory mapped region.
14 - reg: Physical base address of the IP registers and length of memory mapped region.
32 - reg: Physical base address of the IP registers and length of memory mapped region.
48 - reg: Physical base address of the IP registers and length of memory mapped region.
49 - reg-names: names of the mapped memory regions listed in regs property in
60 - reg: Physical base address of the IP registers and length of memory mapped region.
61 - reg-names: names of the mapped memory regions listed in regs property in
76 - reg: Physical base address of the IP registers and length of memory mapped region.
77 - reg-names: names of the mapped memory regions listed in regs property in
89 - reg: Physical base address of the IP registers and length of memory mapped region.
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux.txt | 19 - reg : The sub-bus number.
29 reg = <0x11800 0x00001900 0x0 0x40>;
45 reg = <2>;
50 reg = <1>;
51 marvell,reg-init = <3 0x10 0 0x5777>,
59 reg = <2>;
60 marvell,reg-init = <3 0x10 0 0x5777>,
68 reg = <3>;
69 marvell,reg-init = <3 0x10 0 0x5777>,
77 reg = <4>;
[all …]
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| D | mdio-mux-gpio.txt | 19 reg = <0x11800 0x00001900 0x0 0x40>;
35 reg = <2>;
40 reg = <1>;
41 marvell,reg-init = <3 0x10 0 0x5777>,
49 reg = <2>;
50 marvell,reg-init = <3 0x10 0 0x5777>,
58 reg = <3>;
59 marvell,reg-init = <3 0x10 0 0x5777>,
67 reg = <4>;
68 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 19 - reg : First resource shall be the CPU bus PMU resource.
24 - reg : First resource shall be the L3C PMU resource.
28 - reg : First resource shall be the IOB PMU resource.
32 - reg : First resource shall be the MCB PMU resource.
37 - reg : First resource shall be the MC PMU resource.
43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.txt | 32 - reg:
36 - reg-names:
38 register range as mentioned in 'reg' above, and will typically contain
80 reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;
81 reg-names = "cs_reg", "mspi", "bspi";
99 reg = <0x0>;
106 reg = <0x0 0x0 0x0 0x100000>;
110 reg = <0x0 0x100000 0x0 0x10000>;
114 reg = <0x0 0x110000 0x0 0x10000>;
118 reg = <0x0 0x120000 0x0 0x400000>;
[all …]
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| /Documentation/devicetree/bindings/ipmi/ |
| D | ipmi-smic.txt | 6 - reg: Address and length of the register set for the device
11 - reg-size - The size of the register. Defaults to 1
12 - reg-spacing - The number of bytes between register starts. Defaults to 1
13 - reg-shift - The amount to shift the registers to the right to get the data
21 reg = <0xfff3a000 0x1000>;
23 reg-size = <4>;
24 reg-spacing = <4>;
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
47 reg = <0x00000004 0x00100100 0x100>;
48 dcr-reg = <0x060 0x020>;
65 - reg : <registers mapping>
72 reg = <0x00000004 0x00200000 0x400>;
[all …]
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | megachips-stdpxxxx-ge-b850v3-fw.txt | 21 - reg : I2C bus address
24 - ports : One input port(reg = <0>) and one output port(reg = <1>)
28 - reg : I2C bus address
29 - ports : One input port(reg = <0>) and one output port(reg = <1>)
41 reg = <0x73>;
51 reg = <0>;
57 reg = <1>;
70 reg = <0x72>;
77 reg = <0>;
84 reg = <1>;
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| /Documentation/devicetree/bindings/nvmem/ |
| D | lpc1857-eeprom.txt | 5 - reg: Must contain an entry with the physical base address and length
6 for each entry in reg-names.
7 - reg-names: Must include the following entries.
8 - reg: EEPROM registers.
21 reg = <0x4000e000 0x1000>,
23 reg-names = "reg", "mem";
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| /Documentation/devicetree/bindings/sound/ |
| D | brcm,cygnus-audio.txt | 7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
23 - reg: The index of ssp port interface to use
31 reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
32 reg-names = "aud", "i2s_in";
49 reg = <0>;
53 reg = <1>;
57 reg = <2>;
61 reg = <3>;
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 23 - reg : First resource shall be the CPU bus (PCP) resource.
29 - reg : First resource shall be the memory controller unit
36 - reg : First resource shall be the PMD resource.
42 - reg : First resource shall be the L3 EDAC resource.
48 - reg : First resource shall be the SoC EDAC resource.
53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
[all …]
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| D | socfpga-eccmgr.txt | 18 - reg : Address and size for ECC error interrupt clear registers.
25 - reg : Address and size for ECC error interrupt clear registers.
40 reg = <0xffd08140 0x4>;
46 reg = <0xffd08144 0x4>;
74 - reg : Address and size for ECC error interrupt clear registers.
81 - reg : Address and size for ECC block registers.
88 - reg : Address and size for ECC block registers.
96 - reg : Address and size for ECC block registers.
104 - reg : Address and size for ECC block registers.
112 - reg : Address and size for ECC block registers.
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 10 - reg : DMA General Status Register, i.e. DGSR which contains
20 - reg : DMA channel specific registers
33 reg = <0x82a8 4>;
41 reg = <0 0x80>;
48 reg = <0x80 0x80>;
55 reg = <0x100 0x80>;
62 reg = <0x180 0x80>;
76 - reg : DMA General Status Register, i.e. DGSR which contains
87 - reg : DMA channel specific registers
95 reg = <0x21300 4>;
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | st-fsm.txt | 5 - reg : Contains register's location and length.
6 - reg-names : Should contain the reg names "spi-fsm"
12 - st,boot-device-reg : Address of the aforementioned boot-device register(s)
18 reg = <0xfe902000 0x1000>;
19 reg-names = "spi-fsm";
22 st,boot-device-reg = <0x958>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,pm8xxx-xoadc.txt | 14 - reg: should contain the ADC base address in the PMIC, typically
49 reg = <0x00 0x0c>;
53 reg = <0x00 0x0d>;
57 reg = <0x00 0x0f>;
61 and only need to have these reg values: they are by hardware definition
70 - reg: should contain the hardware channel number in the range
106 reg = <0x197>;
113 reg = <0x00 0x00>;
116 reg = <0x00 0x01>;
119 reg = <0x00 0x02>;
[all …]
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