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/Documentation/devicetree/bindings/regulator/
Dfixed-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fixed Voltage regulators
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 Any property defined as part of the core regulator binding, defined in
15 regulator.yaml, can also be used. However a fixed voltage regulator is
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
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Dqcom,rpmh-regulator.txt3 rpmh-regulator devices support PMIC regulator management via the Voltage
4 Regulator Manager (VRM) and Oscillator Buffer (XOB) RPMh accelerators. The APPS
7 parameters for a given regulator: enable state, output voltage, and operating
8 mode. The XOB allows changing only a single parameter for a given regulator:
10 enable state of any PMIC peripheral. It is used for clock buffers, low-voltage
11 switches, and LDO/SMPS regulators which have a fixed voltage and mode.
19 RPMh device node. The second level describes each regulator within the PMIC
23 The names used for regulator nodes must match those supported by a given PMIC.
24 Supported regulator node names:
25 PM8005: smps1 - smps4
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/Documentation/devicetree/bindings/mfd/
Drohm,bd70528-pmic.txt3 BD70528MWV is an ultra-low quiescent current general purpose, single-chip,
4 power management IC for battery-powered portable devices. The IC
5 integrates 3 ultra-low current consumption buck converters, 3 LDOs and 2
6 LED Drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
7 clock gate, high-accuracy VREF for use with an external ADC, flexible
8 dual-input power path, 10 bit SAR ADC for battery temperature monitor and
12 - compatible : Should be "rohm,bd70528"
13 - reg : I2C slave address.
14 - interrupts : The interrupt line the device is connected to.
15 - interrupt-controller : To indicate BD70528 acts as an interrupt controller.
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Drohm,bd71837-pmic.txt4 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. They are
10 https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
12 https://www.rohm.com/datasheet/BD71847AMWV/bd71847amwv-e
15 - compatible : Should be "rohm,bd71837" for bd71837
17 - reg : I2C slave address.
18 - interrupt-parent : Phandle to the parent interrupt controller.
19 - interrupts : The interrupt line the device is connected to.
20 - clocks : The parent clock connected to PMIC. If this is missing
21 32768 KHz clock is assumed.
22 - #clock-cells : Should be 0.
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Dmax8998.txt1 * Maxim MAX8998, National/TI LP3974 multi-function device
3 The Maxim MAX8998 is a multi-function device which includes voltage/current
4 regulators, real time clock, battery charging controller and several
5 other sub-blocks. It is interfaced using an I2C interface. Each sub-block
8 PMIC sub-block
9 --------------
11 The PMIC sub-block contains a number of voltage and current regulators,
13 In addition, it includes a real time clock and battery charging controller
17 - compatible: Should be one of the following:
18 - "maxim,max8998" for Maxim MAX8998
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/Documentation/devicetree/bindings/clock/
Dti,cdce925.txt1 Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
4 This binding uses the common clock binding[1].
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 The driver provides clock sources for each output Y1 through Y5.
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
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Dsilabs,si5341.txt1 Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator.
5 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
7 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
9 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
12 The internal structure of the clock generators can be found in [2].
15 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
28 - compatible: shall be one of the following:
29 "silabs,si5340" - Si5340 A/B/C/D
30 "silabs,si5341" - Si5341 A/B/C/D
31 - reg: i2c device address, usually 0x74
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Dmaxim,max9485.txt1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provice 27.000 MHz
16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; shall be set to 1
20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for Vdd
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/Documentation/devicetree/bindings/iio/adc/
Drenesas,gyroadc.txt1 * Renesas R-Car GyroADC device driver
5 are sampled by the GyroADC block in a round-robin fashion and the result
9 - compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
10 The <soc-specific> should be one of:
11 renesas,r8a7791-gyroadc - for the GyroADC block present
13 renesas,r8a7792-gyroadc - for the GyroADC with interrupt
15 - reg: Address and length of the register set for the device
16 - clocks: References to all the clocks specified in the clock-names
18 Documentation/devicetree/bindings/clock/clock-bindings.txt.
19 - clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
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/Documentation/devicetree/bindings/ufs/
Dufs-mediatek.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
7 contain a phandle reference to UFS M-PHY node.
10 - compatible : Compatible list, contains the following controller:
11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller
13 - reg : Address and length of the UFS register set.
14 - phys : phandle to m-phy.
15 - clocks : List of phandle and clock specifier pairs.
16 - clock-names : List of clock input name strings sorted in the same
18 "ufs": ufshci core control clock.
19 - freq-table-hz : Array of <min max> operating frequencies stored in the same
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Dufshcd-pltfrm.txt3 UFSHC nodes are defined to describe on-chip UFS host controllers.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 - interrupts : <interrupt mapping for UFS host controller IRQ>
17 - reg : <registers mapping>
20 - phys : phandle to UFS PHY node
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/Documentation/devicetree/bindings/display/msm/
Ddsi.txt5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
21 For DSIv2, we need an additional clock:
23 For DSI6G v2.0 onwards, we need also need the clock:
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/Documentation/driver-api/
Dregulator.rst1 .. Copyright 2007-2008 Wolfson Microelectronics
8 Voltage and current regulator API
20 The intention is to allow systems to dynamically control regulator power
27 ``Documentation/power/regulator``.
30 --------
32 The regulator API uses a number of terms which may not be familiar:
34 Regulator
42 Electronic device which consumes power provided by a regulator. These
43 may either be static, requiring only a fixed supply, or dynamic,
44 requiring active management of the regulator at runtime.
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/Documentation/devicetree/bindings/input/
Dpwm-vibrator.txt8 driven at fixed duty cycle. If available this is can be used to increase
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
32 pinctrl-single,pins = <
39 pwm8: dmtimer-pwm {
40 pinctrl-names = "default";
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/Documentation/devicetree/bindings/iio/dac/
Dad5592r.txt4 - compatible: Must be "adi,ad5592r"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: Max SPI frequency to use (< 30000000)
7 - spi-cpol: The AD5592R requires inverse clock polarity (CPOL) mode
10 - compatible: Must be "adi,ad5593r"
11 - reg: I2C address of the device
14 - #address-cells: Should be 1.
15 - #size-cells: Should be 0.
16 - channel nodes:
22 can be found in <dt-bindings/iio/adi,ad5592r.h>.
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/Documentation/devicetree/bindings/display/
Datmel,lcdc.txt2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 "atmel,at32ap-lcdc"
13 - reg : Should contain 1 register ranges(address and length).
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/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
6 and a power line, which are able to change the clock frequency
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
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/Documentation/devicetree/bindings/pinctrl/
Dallwinner,sunxi-pinctrl.txt6 the pins includes drive strength and pull-up.
9 - compatible: Should be one of the following (depending on your SoC):
10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31s-pinctrl"
15 "allwinner,sun6i-a31-r-pinctrl"
16 "allwinner,sun7i-a20-pinctrl"
17 "allwinner,sun8i-a23-pinctrl"
[all …]
/Documentation/devicetree/bindings/usb/
Damlogic,dwc3.txt4 - compatible: depending on the SoC this should contain one of:
5 * amlogic,meson-axg-dwc3
6 * amlogic,meson-gxl-dwc3
7 - clocks: a handle for the "USB general" clock
8 - clock-names: must be "usb_general"
9 - resets: a handle for the shared "USB OTG" reset line
10 - reset-names: must be "usb_otg"
17 - Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
18 - Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
22 compatible = "amlogic,meson-axg-dwc3";
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/Documentation/devicetree/bindings/pci/
Dhost-generic-pci.txt3 Firmware-initialised PCI host controllers and PCI emulations, such as the
4 virtio-pci implementations found in kvmtool and other para-virtualised
5 systems, do not require driver support for complexities such as regulator
6 and clock management. In fact, the controller may not even require the
8 presenting a set of fixed windows describing a subset of IO, Memory and
17 - compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
21 - device_type : Must be "pci".
23 - ranges : As described in IEEE Std 1275-1994, but must provide
24 at least a definition of non-prefetchable memory. One
28 - bus-range : Optional property (also described in IEEE Std 1275-1994)
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/Documentation/arm64/
Darm-acpi.rst22 industry-standard ARMv8 servers, they also apply to more than one operating
24 ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of
29 ----------------
32 exist in Linux for describing non-enumerable hardware, after all. In this
39 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
44 - ACPI’s OSPM defines a power management model that constrains what the
48 - In the enterprise server environment, ACPI has established bindings (such
54 - Choosing a single interface to describe the abstraction between a platform
60 - The new ACPI governance process works well and Linux is now at the same
86 interfaces -- one for Linux and one for Windows.
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/Documentation/hwmon/
Dsysfs-interface.rst5 through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
6 completely chip-independent. It assumes that all the kernel drivers
10 This is a major improvement compared to lm-sensors 2.
22 For this reason, even if we aim at a chip-independent libsensors, it will
37 Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
38 in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
44 All sysfs values are fixed point numbers.
61 to cause an alarm) is chip-dependent.
68 -------------------------------------------------------------------------
71 `[0-*]` denotes any positive number starting from 0
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/Documentation/admin-guide/laptops/
Dthinkpad-acpi.rst9 - Borislav Deianov <borislav@users.sf.net>
10 - Henrique de Moraes Holschuh <hmh@hmh.eng.br>
12 http://ibm-acpi.sf.net/
19 This driver used to be named ibm-acpi until kernel 2.6.21 and release
20 0.13-20070314. It used to be in the drivers/acpi tree, but it was
21 moved to the drivers/misc tree and renamed to thinkpad-acpi for kernel
25 The driver is named "thinkpad-acpi". In some places, like module
29 "tpacpi" is used as a shorthand where "thinkpad-acpi" would be too
33 ------
38 - Fn key combinations
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