Searched +full:reserved +full:- +full:memory (Results 1 – 25 of 191) sorted by relevance
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | reserved-memory.txt | 1 *** Reserved memory regions ***
3 Reserved memory is specified as a node under the /reserved-memory node.
4 The operating system shall exclude reserved memory from normal usage
5 one can create child nodes describing particular reserved (excluded from
6 normal use) memory regions. Such memory regions are usually designed for
9 Parameters for each memory region can be encoded into the device tree
12 /reserved-memory node
13 ---------------------
14 #address-cells, #size-cells (required) - standard definition
15 - Should use the same values as the root node
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| D | xen,shared-memory.txt | 1 * Xen hypervisor reserved-memory binding
3 Expose one or more memory regions as reserved-memory to the guest
5 to be a shared memory area across multiple virtual machines for
8 For each of these pre-shared memory regions, a range is exposed under
9 the /reserved-memory node as a child node. Each range sub-node is named
10 xen-shmem@<address> and has the following properties:
12 - compatible:
13 compatible = "xen,shared-memory-v1"
15 - reg:
16 the base guest physical address and size of the shared memory region
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| D | qcom,cmd-db.txt | 2 ---------
6 is stored in a shared memory region and is loaded by the remote processor.
11 remote processor and made available in the shared memory.
13 The bindings for Command DB is specified in the reserved-memory section in
17 - compatible:
20 Definition: Should be "qcom,cmd-db"
22 - reg:
26 the Command DB in memory.
30 reserved-memory {
32 reserved-memory@85fe0000 {
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| D | qcom,rmtfs-mem.txt | 1 Qualcomm Remote File System Memory binding
3 This binding describes the Qualcomm remote filesystem memory, which serves the
4 purpose of describing the shared memory region used for remote processors to
7 - compatible:
11 "qcom,rmtfs-mem"
13 - reg:
15 Value type: <prop-encoded-array>
16 Definition: must specify base address and size of the memory region,
17 as described in reserved-memory.txt
19 - size:
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| D | ramoops.txt | 5 recovered after a reboot. This is a child-node of "/reserved-memory", and
10 as kernel log messages, or for optional ECC error-correction data. The total
11 size of these optional buffers must fit in the reserved region.
17 At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size"
18 must be set non-zero, but are otherwise optional as listed below.
23 - compatible: must be "ramoops"
25 - reg: region of memory that is preserved between reboots
30 - ecc-size: enables ECC support and specifies ECC buffer size in bytes
33 - record-size: maximum size in bytes of each dump done on oops/panic
36 - console-size: size in bytes of log buffer reserved for kernel messages
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
12 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
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| D | imx-rproc.txt | 1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
17 (See: ../reserved-memory/reserved-memory.txt)
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| D | st-rproc.txt | 1 STMicroelectronics Co-Processor Bindings
2 ----------------------------------------
6 Co-processors can be controlled from the bootloader or the primary OS. If
7 the bootloader starts a co-processor, the primary OS must detect its state
11 - compatible Should be one of:
12 "st,st231-rproc"
13 "st,st40-rproc"
14 - memory-region Reserved memory (See: ../reserved-memory/reserved-memory.txt)
15 - resets Reset lines (See: ../reset/reset.txt)
16 - reset-names Must be "sw_reset" and "pwr_reset"
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| D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
9 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
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| D | stm32-rproc.txt | 2 -----------------------------------
7 - compatible: Must be "st,stm32mp1-m4"
8 - reg: Address ranges of the RETRAM and MCU SRAM memories used by the
10 - resets: Reference to a reset controller asserting the remote processor.
11 - st,syscfg-holdboot: Reference to the system configuration which holds the
16 - st,syscfg-tz: Reference to the system configuration which holds the RCC trust
23 - interrupts: Should contain the watchdog interrupt
24 - mboxes: This property is required only if the rpmsg/virtio functionality
26 - a channel (a) used to communicate through virtqueues with the
28 Bi-directional channel:
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| /Documentation/devicetree/bindings/media/ |
| D | s5p-mfc.txt | 10 - compatible : value should be either one among the following
11 (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
12 (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
13 (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
14 (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
15 (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
16 (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
18 - reg : Physical base address of the IP registers and length of memory
21 - interrupts : MFC interrupt number to the CPU.
22 - clocks : from common clock binding: handle to mfc clock.
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| D | aspeed-video.txt | 7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine"
9 - reg: contains the offset and length of the VE memory region
10 - clocks: clock specifiers for the syscon clocks associated with
11 the VE (ordering must match the clock-names property)
12 - clock-names: "vclk" and "eclk"
13 - resets: reset specifier for the syscon reset associated with
15 - interrupts: the interrupt associated with the VE on this platform
18 - memory-region:
19 phandle to a memory region to allocate from, as defined in
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| D | mediatek-vpu.txt | 7 - compatible: "mediatek,mt8173-vpu"
8 - reg: Must contain an entry for each entry in reg-names.
9 - reg-names: Must include the following entries:
12 - interrupts: interrupt number to the cpu.
13 - clocks : clock name from clock manager
14 - clock-names: must be main. It is the main clock of VPU
17 - memory-region: phandle to a node describing memory (see
18 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
19 to be used for VPU extended memory; if not present, VPU may be located
20 anywhere in the memory
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| /Documentation/powerpc/ |
| D | firmware-assisted-dump.rst | 2 Firmware-Assisted Dump
7 The goal of firmware-assisted dump is to enable the dump of
8 a crashed system, and to do so from a fully-reset system, and
12 - Firmware-Assisted Dump (FADump) infrastructure is intended to replace
14 - Fadump uses the same firmware interfaces and memory reservation model
16 - Unlike phyp dump, FADump exports the memory dump through /proc/vmcore
19 - Unlike phyp dump, userspace tool does not need to refer any sysfs
21 - Unlike phyp dump, FADump allows user to release all the memory reserved
23 - Once enabled through kernel boot parameter, FADump can be
28 Comparing with kdump or other strategies, firmware-assisted
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | qman.txt | 3 Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
7 - QMan Node
8 - QMan Private Memory Nodes
9 - Example
13 The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
16 flow-level queuing, is also responsible for congestion management functions such
22 - compatible
26 May include "fsl,<SoC>-qman"
28 - reg
30 Value type: <prop-encoded-array>
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| D | bman.txt | 3 Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
7 - BMan Node
8 - BMan Private Memory Node
9 - Example
13 The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
20 - compatible
24 May include "fsl,<SoC>-bman"
26 - reg
28 Value type: <prop-encoded-array>
34 - interrupts
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| /Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
22 -------------------
26 - compatible: "intel,stratix10-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
31 phandle to the reserved memory node. See
32 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
36 -------
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.txt | 1 Generic on-chip SRAM
3 Simple IO memory regions to be managed by the genalloc API.
7 - compatible : mmio-sram or atmel,sama5d2-securam
9 - reg : SRAM iomem address range
12 ---------------------
14 Each child of the sram node specifies a region of reserved memory. Each
16 reserved memory.
18 Following the generic-names recommended practice, node names should
24 - #address-cells, #size-cells : should use the same values as the root node
25 - ranges : standard definition, should translate from local addresses
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| /Documentation/xtensa/ |
| D | atomctl.rst | 10 can do Atomic Transactions to the memory internally.
12 2. With and without An Intelligent Memory Controller which
19 On the FPGA Cards we typically simulate an Intelligent Memory controller
21 Memory controller we let it to the atomic operations internally while
22 doing a Cached (WB) transaction and use the Memory RCW for un-cached
25 For systems without an coherent cache controller, non-MX, we always
26 use the memory controllers RCW, thought non-MX controlers likely
29 CUSTOMER-WARNING:
30 Virtually all customers buy their memory controllers from vendors that
31 don't support atomic RCW memory transactions and will likely want to
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| /Documentation/arm64/ |
| D | booting.rst | 13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
82 u64 res2 = 0; /* reserved */
83 u64 res3 = 0; /* reserved */
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.txt | 2 --------------------------
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
5 acts as directory-based coherency manager.
9 --------------------
10 - compatible: Should be "sifive,fu540-c000-ccache" and "cache"
12 - cache-block-size: Specifies the block size in bytes of the cache.
15 - cache-level: Should be set to 2 for a level 2 cache
17 - cache-sets: Specifies the number of associativity sets of the cache.
20 - cache-size: Specifies the size in bytes of the cache. Should be 2097152
22 - cache-unified: Specifies the cache is a unified cache
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| /Documentation/devicetree/bindings/dsp/ |
| D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
26 - description: ipg clock
27 - description: ocram clock
28 - description: core clock
30 clock-names:
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| /Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 4 - compatible
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
15 - clocks: clock number used to generate the pixel clock
17 - resets: reset line that must be released to use the GFX device
19 - memory-region:
20 Phandle to a memory region to allocate from, as defined in
21 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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| /Documentation/sparc/oradax/ |
| D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
4 Copyright © 2008, 2015 Oracle and/or its affiliates. All rights reserved.
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
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| /Documentation/devicetree/bindings/display/ |
| D | arm,hdlcd.txt | 9 - compatible: "arm,hdlcd"
10 - reg: Physical base address and length of the controller's registers.
11 - interrupts: One interrupt used by the display controller to notify the
14 - clocks: A list of phandle + clock-specifier pairs, one for each
15 entry in 'clock-names'.
16 - clock-names: A list of clock names. For HDLCD it should contain:
17 - "pxlclk" for the clock feeding the output PLL of the controller.
19 Required sub-nodes:
20 - port: The HDLCD connection to an encoder chip. The connection is modeled
25 - memory-region: phandle to a node describing memory (see
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