Searched full:sec (Results 1 – 25 of 128) sorted by relevance
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
10 - interrupts : the SEC's interrupt number
17 should be encoded following the SEC's Descriptor Header Dword
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
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| D | fsl-sec6.txt | 1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
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| D | fsl-sec4.txt | 2 SEC 4 Device Tree Binding
7 -SEC 4 Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
23 SEC 4 h/w can process requests from 2 types of sources.
24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
25 2. Job Rings (HW interface between cores & SEC 4 registers).
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
42 SEC 4 Node
46 Node defines the base address of the SEC 4 block.
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| D | hisilicon,hip07-sec.txt | 1 * Hisilicon hip07 Security Accelerator (SEC)
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
16 Interrupt 0 is for the SEC unit error queue.
22 - iommus: The SEC units are behind smmu-v3 iommus.
28 compatible = "hisilicon,hip07-sec";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | atmel-wdt.txt | 12 - timeout-sec: contains the watchdog timeout in seconds.
14 - atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
17 - atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
18 seconds. This value must be smaller than the max-heartbeat-sec value.
44 timeout-sec = <15>;
49 atmel,max-heartbeat-sec = <16>;
50 atmel,min-heartbeat-sec = <0>;
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| D | brcm,bcm2835-pm-wdog.txt | 10 - timeout-sec : Contains the watchdog timeout in seconds
17 timeout-sec = <10>;
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| D | pnx4008-wdt.txt | 9 - timeout-sec: contains the watchdog timeout in seconds.
16 timeout-sec = <10>;
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| D | sirfsoc_wdt.txt | 9 - timeout-sec : Contains the watchdog timeout in seconds
17 timeout-sec = <30>;
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| D | sigma,smp8642-wdt.txt | 9 - timeout-sec: watchdog timeout in seconds
17 timeout-sec = <30>;
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| D | stericsson-coh901327.txt | 10 - timeout-sec: contains the watchdog timeout in seconds.
18 timeout-sec = <60>;
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| D | ziirave-wdt.txt | 8 - timeout-sec: Watchdog timeout value in seconds.
17 timeout-sec = <30>;
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| D | meson-wdt.txt | 13 - timeout-sec: contains the watchdog timeout in seconds.
20 timeout-sec = <10>;
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| D | ts4800-wdt.txt | 11 - timeout-sec: contains the watchdog timeout in seconds.
23 timeout-sec = <10>;
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| D | qcom,pm8916-wdt.txt | 10 - timeout-sec : Watchdog timeout value in seconds.
25 timeout-sec = <10>;
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| D | sprd-wdt.txt | 7 - timeout-sec : Contain the default watchdog timeout in seconds.
16 timeout-sec = <12>;
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| D | digicolor-wdt.txt | 16 - timeout-sec : Contains the watchdog timeout in seconds
24 timeout-sec = <15>;
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| D | fsl-imx7ulp-wdt.txt | 10 - timeout-sec : Contains the watchdog timeout in seconds
21 timeout-sec = <40>;
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| D | mtk-wdt.txt | 17 - timeout-sec: contains the watchdog timeout in seconds.
24 timeout-sec = <10>;
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| D | davinci-wdt.txt | 8 - timeout-sec : Contains the watchdog timeout in seconds
22 timeout-sec = <30>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 11 - interrupt-names: interrupt line names eg. "sec" "alarm"
14 - calibration: calibration value for 1 sec period which will
23 interrupt-names = "alarm", "sec";
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| /Documentation/usb/ |
| D | ehci.rst | 11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
155 them. The 480 Mbit/sec "raw transfer rate" is obeyed by all devices,
165 So more than 50 MByte/sec is available for bulk transfers, when both
168 approach the quoted 480 MBit/sec transfer rate.
174 20 MByte/sec transfer rates. This is of course subject to change;
178 at around 28 MByte/sec aggregate transfer rate. While this is clearly
179 enough for a single device at 20 MByte/sec, putting three such devices
180 onto one bus does not get you 60 MByte/sec. The issue appears to be
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| /Documentation/hwmon/ |
| D | asc7621.rst | 277 * 0 0 Sec. (no Smoothing) (default)
278 * 1 0.25 Sec.
279 * 2 0.5 Sec.
280 * 3 1.0 Sec.
281 * 4 2.0 Sec.
282 * 5 4.0 Sec.
283 * 6 8.0 Sec.
284 * 7 0.0 Sec.
302 0 0.25 Sec.
303 1 1.1 Sec.
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| /Documentation/watchdog/ |
| D | mlx-wdt.rst | 17 e.g. timeout 20 sec will be rounded up to 32768 msec.
18 The maximum timeout period is 32 sec (32768 msec.),
22 Actual HW timeout is defined in sec. and it's the same as
24 Maximum timeout is 255 sec.
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| /Documentation/media/uapi/dvb/ |
| D | frontend.rst | 35 - Satellite Equipment Control (SEC) [#f1]_.
49 Control (SEC) allows to power control and to send/receive signals to
52 Horn (LNBf). It supports the DiSEqC and V-SEC protocols. The DiSEqC
53 (digital SEC) specification is available at
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| /Documentation/media/v4l-drivers/ |
| D | max2175.rst | 53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
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