Searched +full:sifive +full:- +full:blocks (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.txt | 1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
17 Please refer to sifive-blocks-ip-versioning.txt for details.
18 - reg: physical base address and length of the controller's registers
19 - clocks: Should contain a clock identifier for the PWM's parent clock.
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.txt | 1 SiFive SPI controller Device Tree Bindings
2 ------------------------------------------
5 - compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>".
7 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
8 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
10 Please refer to sifive-blocks-ip-versioning.txt for details
11 - reg : Physical base address and size of SPI registers map
13 - interrupts : Must contain one entry
14 - interrupt-parent : Must be core interrupt controller
15 - clocks : Must reference the frequency given to the controller
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| /Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: /schemas/serial.yaml#
20 - const: sifive,fu540-c000-uart
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
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