| /Documentation/devicetree/bindings/mfd/ |
| D | mfd.txt | 1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
6 A typical MFD can be:
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
14 - A range of memory registers containing "miscellaneous system registers" also
20 - compatible : "simple-mfd" - this signifies that the operating system should
21 consider all subnodes of the MFD device as separate devices akin to how
22 "simple-bus" indicates when to see subnodes as children for a simple
23 memory-mapped bus. For more complex devices, when the nexus driver has to
28 - ranges: Describes the address mapping relationship to the parent. Should set
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| D | aspeed-scu.txt | 5 - compatible: One of:
6 "aspeed,ast2400-scu", "syscon", "simple-mfd"
7 "aspeed,ast2500-scu", "syscon", "simple-mfd"
9 - reg: contains the offset and length of the SCU memory region
10 - #clock-cells: should be set to <1> - the system controller is also a
12 - #reset-cells: should be set to <1> - the system controller is also a
18 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
20 #clock-cells = <1>;
21 #reset-cells = <1>;
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| D | atmel-tcb.txt | 2 - compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
4 - reg: Should contain registers location and length
5 - #address-cells: has to be 1
6 - #size-cells: has to be 0
7 - interrupts: Should contain all interrupts for the TC block
10 - clock-names: tuple listing input clock names.
13 - clocks: phandles to input clocks.
17 - compatible: Should be "atmel,tcb-timer"
18 - reg: Should contain the TCB channels to be used. If the
19 counter width is 16 bits (at91rm9200-tcb), two consecutive
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| D | aspeed-lpc.txt | 5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
11 The LPC controller is represented as a multi-function device to account for the
24 APB-to-LPC bridging amonst other functions.
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
39 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
40 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
46 - compatible: One of:
47 "aspeed,ast2400-lpc", "simple-mfd"
48 "aspeed,ast2500-lpc", "simple-mfd"
50 - reg: contains the physical address and length values of the Aspeed
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| /Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 7 - compatible: "mscc,ocelot"
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
41 compatible = "mscc,ocelot-cpu-syscon", "syscon";
52 - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
53 - reg : Should contain registers location and length
57 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
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| /Documentation/devicetree/bindings/clock/ |
| D | oxnas,stdclk.txt | 4 Please also refer to clock-bindings.txt in this directory for common clock
8 - compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
9 For OX820, should be "oxsemi,ox820-stdclk"
10 - #clock-cells: 1, see below
13 - compatible: For OX810SE, should be
14 "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
16 "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
20 sys: sys-ctrl@000000 {
21 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
25 compatible = "oxsemi,ox810se-stdclk";
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| D | amlogic,gxbb-clkc.txt | 8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
15 - clocks : list of clock phandle, one for each entry clock-names.
16 - clock-names : should contain the following:
19 - #clock-cells: should be 1.
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| D | uniphier-clock.txt | 5 ------------
8 - compatible: should be one of the following:
9 "socionext,uniphier-ld4-clock" - for LD4 SoC.
10 "socionext,uniphier-pro4-clock" - for Pro4 SoC.
11 "socionext,uniphier-sld8-clock" - for sLD8 SoC.
12 "socionext,uniphier-pro5-clock" - for Pro5 SoC.
13 "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
14 "socionext,uniphier-ld11-clock" - for LD11 SoC.
15 "socionext,uniphier-ld20-clock" - for LD20 SoC.
16 "socionext,uniphier-pxs3-clock" - for PXs3 SoC
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| D | amlogic,gxbb-aoclkc.txt | 4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
15 - clocks: list of clock phandle, one for each entry clock-names.
16 - clock-names: should contain the following:
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| /Documentation/devicetree/bindings/reset/ |
| D | oxnas,reset.txt | 8 - compatible: For OX810SE, should be "oxsemi,ox810se-reset"
9 For OX820, should be "oxsemi,ox820-reset"
10 - #reset-cells: 1, see below
13 - compatible: For OX810SE, should be :
14 "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
16 "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
18 Reset indices are in dt-bindings include files :
19 - For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
20 - For OX820: include/dt-bindings/reset/oxsemi,ox820.h
24 sys: sys-ctrl@000000 {
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| D | uniphier-reset.txt | 5 ------------
8 - compatible: should be one of the following:
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | aspeed,ast2500-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
21 Documentation/devicetree/bindings/mfd/syscon.txt
25 const: aspeed,ast2500-pinctrl
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| D | aspeed,ast2400-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2400-scu", "syscon", "simple-mfd"
20 Documentation/devicetree/bindings/mfd/syscon.txt
24 const: aspeed,ast2400-pinctrl
34 - $ref: "/schemas/types.yaml#/definitions/string"
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| D | marvell,armada-37xx-pinctrl.txt | 12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
33 - pins 20-24
34 - functions jtag, gpio
37 - pins 8-10
38 - functions sdio, gpio
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| /Documentation/devicetree/bindings/nvmem/ |
| D | snvs-lpgpr.txt | 2 and i.MX7 Secure Non-Volatile Storage.
4 This DT node should be represented as a sub-node of a "syscon",
5 "simple-mfd" node.
8 - compatible: should be one of the fallowing variants:
9 "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
10 "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
11 "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S
15 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
18 snvs_lpgpr: snvs-lpgpr {
19 compatible = "fsl,imx6q-snvs-lpgpr";
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| /Documentation/devicetree/bindings/misc/ |
| D | aspeed-p2a-ctrl.txt | 2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - memory-region: A phandle to a reserved_memory region to be used for the PCI
24 The p2a-control node should be the child of a syscon node with the required
27 - compatible : Should be one of the following:
28 "aspeed,ast2400-scu", "syscon", "simple-mfd"
29 "aspeed,ast2500-scu", "syscon", "simple-mfd"
35 ----------
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| /Documentation/devicetree/bindings/arm/ |
| D | syna.txt | 3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
19 ---------------------------------------------------------------
34 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
36 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
42 model = "Sony NSZ-GS7";
43 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
54 - compatible: should be "marvell,berlin-cpu-ctrl"
55 - reg: address and length of the register set
59 cpu-ctrl@f7dd0000 {
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| /Documentation/devicetree/bindings/power/reset/ |
| D | syscon-reboot-mode.txt | 3 This driver gets reboot mode magic value form reboot-mode driver
8 This DT node should be represented as a sub-node of a "syscon", "simple-mfd"
12 - compatible: should be "syscon-reboot-mode"
13 - offset: offset in the register map for the storage register (in bytes)
16 - mask: bits mask of the bits in the register to store the reboot mode magic value,
19 The rest of the properties should follow the generic reboot-mode description
20 found in reboot-mode.txt
24 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
27 reboot-mode {
28 compatible = "syscon-reboot-mode";
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | ap806-system-controller.txt | 6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP806 system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
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| /Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-gx-pwrc.txt | 7 ----------------
16 ---------------------
19 - compatible: should be one of the following :
20 - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
21 - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
22 - #power-domain-cells: should be 0
23 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
24 - resets: phandles to the reset lines needed for this power demain sequence
26 - clocks: from common clock binding: handle to VPU and VAPB clocks
27 - clock-names: from common clock binding: must contain "vpu", "vapb"
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| /Documentation/devicetree/bindings/watchdog/ |
| D | uniphier-wdt.txt | 6 - compatible: should be "socionext,uniphier-wdt"
11 compatible = "socionext,uniphier-ld11-sysctrl",
12 "simple-mfd", "syscon";
16 compatible = "socionext,uniphier-wdt";
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| D | ts4800-wdt.txt | 4 - compatible: must be "technologic,ts4800-wdt"
5 - syscon: phandle / integer array that points to the syscon node which
7 - phandle to FPGA's syscon
8 - offset to the watchdog register
11 - timeout-sec: contains the watchdog timeout in seconds.
16 compatible = "syscon", "simple-mfd";
18 reg-io-width = <2>;
21 compatible = "technologic,ts4800-wdt";
23 timeout-sec = <10>;
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| /Documentation/devicetree/bindings/input/ |
| D | cpcap-pwrbutton.txt | 4 chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt.
6 This module provides a simple power button event via an Interrupt.
9 - compatible: should be one of the following
10 - "motorola,cpcap-pwrbutton"
11 - interrupts: irq specifier for CPCAP's ON IRQ
17 compatible = "motorola,cpcap-pwrbutton";
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| D | twl4030-pwrbutton.txt | 4 chip see Documentation/devicetree/bindings/mfd/twl-familly.txt.
6 This module provides a simple power button event via an Interrupt.
9 - compatible: should be one of the following
10 - "ti,twl4030-pwrbutton": For controllers compatible with twl4030
11 - interrupts: should be one of the following
12 - <8>: For controllers compatible with twl4030
18 compatible = "ti,twl4030-pwrbutton";
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| /Documentation/devicetree/bindings/mips/lantiq/ |
| D | rcu.txt | 5 where each sub-device has it's own set of registers.
14 -------------------------------------------------------------------------------
16 - compatible : The first and second values must be:
17 "lantiq,xrx200-rcu", "simple-mfd", "syscon"
18 - reg : The address and length of the system control registers
21 -------------------------------------------------------------------------------
24 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
27 big-endian;
29 reset0: reset-controller@10 {
30 compatible = "lantiq,xrx200-reset";
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