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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.txt | 4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
23 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
24 more than one pin, for which "pinctrl-single,function-mask" property specifies
27 - pinctrl-single,drive-strength : array of value that are used to configure
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | ak4613.txt | 11 - asahi-kasei,in1-single-end : Boolean. Indicate input / output pins are single-ended.
12 - asahi-kasei,in2-single-end rather than differential.
13 - asahi-kasei,out1-single-end
14 - asahi-kasei,out2-single-end
15 - asahi-kasei,out3-single-end
16 - asahi-kasei,out4-single-end
17 - asahi-kasei,out5-single-end
18 - asahi-kasei,out6-single-end
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| D | pcm3060.txt | 14 - ti,out-single-ended: "true" if output is single-ended;
22 ti,out-single-ended = "true";
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| D | cs42l52.txt | 23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
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| D | max98373.txt | 24 - maxim,interleave-mode : For cases where a single combined channel
26 to share a single data output channel on alternating frames.
28 on a single output channel.
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 127 # Microchip 7-bit Single I2C Digital POT (5k)
129 # Microchip 7-bit Single I2C Digital POT (10k)
131 # Microchip 7-bit Single I2C Digital POT (50k)
133 # Microchip 7-bit Single I2C Digital POT (100k)
135 # Microchip 7-bit Single I2C Digital POT (5k)
137 # Microchip 7-bit Single I2C Digital POT (10k)
139 # Microchip 7-bit Single I2C Digital POT (50k)
141 # Microchip 7-bit Single I2C Digital POT (100k)
143 # Microchip 7-bit Single I2C Digital POT (5k)
145 # Microchip 7-bit Single I2C Digital POT (10k)
[all …]
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| /Documentation/hwmon/ |
| D | pcf8591.rst | 29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
39 - mode 2 : single ended and differential mixed
40 Pins AIN0 and AIN1 are single ended inputs for channels 0 and 1
59 - 0 = four single ended inputs
61 - 2 = single ended and differential mixed
89 from 0 to 255 for single ended inputs and -128 to +127 for differential inputs
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
19 - interrupts : Should be single bit error interrupt, then double bit error
27 - interrupts : Should be single bit error interrupt, then double bit error
63 - interrupts : Should be single bit error interrupt, then double bit error
75 - interrupts : Should be single bit error interrupt, then double bit error
82 - interrupts : Should be single bit error interrupt, then double bit error
90 - interrupts : Should be single bit error interrupt, then double bit error
98 - interrupts : Should be single bit error interrupt, then double bit error
106 - interrupts : Should be single bit error interrupt, then double bit error
114 - interrupts : Should be single bit error interrupt, then double bit error
[all …]
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| /Documentation/media/uapi/v4l/ |
| D | planar-apis.rst | 13 Single- and multi-planar APIs
27 depending on whether single- or multi-planar API is being used. An
41 can handle all single-planar formats as well (as long as they are passed
42 in multi-planar API structures), while the single-planar API cannot
46 Calls that distinguish between single and multi-planar APIs
52 single- and multi-planar formats.
59 FourCC codes from the existing single-planar ones.
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| /Documentation/driver-api/ |
| D | edac.rst | 32 A physical connector on the motherboard that accepts a single memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
70 accessed. Common chip-select rows for single channel are 64 bits, for
75 * Single-Ranked stick
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
99 All of the memory sticks that are required for a single memory access or
100 all of the memory sticks spanned by a chip-select row. A single socket
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ina3221.txt | 9 - ti,single-shot: This chip has two power modes: single-shot (chip takes one
13 but the single-shot mode is more power-friendly and useful
16 If this property is present, the single-shot mode will be
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| D | adc128d818.txt | 6 - Mode 0: 7 single-ended voltage readings (IN0-IN6),
8 - Mode 1: 8 single-ended voltage readings (IN0-IN7),
13 - Mode 3: 4 single-ended voltage readings (IN0-IN3),
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| /Documentation/devicetree/bindings/iio/accel/ |
| D | lis302.txt | 23 - st,click-single-{x,y,z}: if present, tells the device to issue an
24 interrupt on single click events on the
74 st,click-single-x;
75 st,click-single-y;
76 st,click-single-z;
98 st,click-single-x;
99 st,click-single-y;
100 st,click-single-z;
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-intel_th-devices-msc | 12 - "single", for contiguous buffer mode (high-order alloc);
25 Description: (RW) Configure MSC buffer size for "single" or "multi" modes.
26 In single mode, this is a single number of pages, has to be
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| /Documentation/scsi/ |
| D | bfa.txt | 16 1657:0017:1657:0014 415 4Gbps single port FC HBA
17 1657:0017:1657:0014 815 8Gbps single port FC HBA
18 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
19 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
22 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
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| /Documentation/filesystems/ |
| D | inotify.txt | 36 There are other good arguments. With a single fd, there is a single
37 item to block on, which is mapped to a single queue of events. The single
43 which happened first. A single queue trivially gives you ordering. Such
48 versus just one. It is a lot messier in the kernel. A single, linear
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| /Documentation/devicetree/bindings/dma/ |
| D | uniphier-mio-dmac.txt | 10 - clocks: a single clock specifier.
11 - #dma-cells: should be <1>. The single cell represents the channel index.
25 The first two channels share a single interrupt line.
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | thine,thc63lvd1024.txt | 5 to parallel data outputs. The chip supports single/dual input/output modes,
8 Single or dual operation mode, output data mapping and DDR output modes are
31 The device can operate in single-link mode or dual-link mode. In single-link
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| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra186-bpmp-i2c.txt | 21 Single-cell integer.
24 Single-cell integer.
27 Single-cell integer.
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| /Documentation/fb/ |
| D | viafb.rst | 67 - 0 : Resolution: 640x480, Channel: single, Dithering: Enable
68 - 1 : Resolution: 800x600, Channel: single, Dithering: Enable
69 - 2 : Resolution: 1024x768, Channel: single, Dithering: Enable (default)
70 - 3 : Resolution: 1280x768, Channel: single, Dithering: Enable
75 - 8 : Resolution: 800x480, Channel: single, Dithering: Enable
77 - 10: Resolution: 1024x768, Channel: single, Dithering: Disable
79 - 12: Resolution: 1280x768, Channel: single, Dithering: Disable
83 - 16: Resolution: 1366x768, Channel: single, Dithering: Disable
84 - 17: Resolution: 1024x600, Channel: single, Dithering: Enable
86 - 19: Resolution: 1280x800, Channel: single, Dithering: Enable
[all …]
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
48 "pinctrl-single";
54 pinctrl-single,register-width = <16>;
55 pinctrl-single,function-mask = <0xff1f>;
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,ceu.txt | 7 The interface supports a single parallel input with data bus width of 8 or 16
17 The CEU supports a single parallel input and should contain a single 'port'
18 subnode with a single 'endpoint'. Connection to input devices are modeled
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| /Documentation/ |
| D | atomic_bitops.txt | 6 operating on single bits in a bitmap that are atomic.
12 The single bit operations are:
69 Since a platform only has a single means of achieving atomic operations
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| /Documentation/devicetree/bindings/display/panel/ |
| D | tianma,tm070rvhg71.txt | 5 - power-supply: single regulator to provide the supply voltage
11 This panel needs single power supply voltage. Its backlight is conntrolled
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| D | auo,g070vvn01.txt | 6 - power-supply: single regulator to provide the supply voltage
11 This panel needs single power supply voltage. Its backlight is conntrolled
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